Solid-state imaging apparatus, method for driving the same, and imaging apparatus

Patent metadata

Field	Value
Publication number	US-9419052-B2
Application number	US-201414554038-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	May 30, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A solid-state imaging apparatus includes a plurality of pixel cells arranged in a pixel array unit, a vertical signal line and a pixel power supply line each connected to a source electrode and a drain electrode of an amplifying transistor, a Pch transistor for supplying potential AVDD to the vertical signal line, a Pch transistor for supplying potential PBIAS_H higher than the potential AVDD to the vertical signal line, a Pch transistor for supplying the potential PBIAS_H to the pixel power supply line, wherein while the transfer transistor is turned ON and transfers signal charges photoelectrically converted by a photodiode to the floating diffusion portion, the Pch transistors are turned ON and the potential PBIAS_H is applied to the vertical signal line and the pixel power supply line.

First claim

The invention claimed is:

1. A solid-state imaging apparatus comprising:
a pixel array unit in which a plurality of pixel cells are arranged in a matrix, each of the plurality of the pixel cells including a photoelectric conversion element, a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion element to a floating diffusion, a reset transistor that resets the floating diffusion, and an amplifying transistor that outputs an amplified signal corresponding to an amount of the signal charges;
a vertical signal line that is connected to a source electrode of the amplifying transistor and receives an output of the amplifying transistor;
a pixel power supply line that is connected to a drain electrode of the amplifying transistor;
a first control transistor for supplying a first potential to the vertical signal line;
a second control transistor for supplying a second potential higher than the first potential to the vertical signal line; and
a third control transistor for supplying the second potential to the pixel power supply line,
wherein, during a period in which the transfer transistor is turned ON and transfers the signal charges to the floating diffusion, the second control transistor and the third control transistor are turned ON and the second potential is applied to the vertical signal line and the pixel power supply line.

2. The solid-state imaging apparatus according to claim 1 , further comprising:
a constant current source transistor that is provided on the vertical signal line and forms a source follower with the amplifying transistor; and
a fourth control transistor that controls conduction and non-conduction between the vertical signal line and the constant current source transistor,
wherein, during a period in which at least the second control transistor and the third control transistor are ON, the fourth control transistor is OFF.

3. The solid-state imaging apparatus according to claim 1 ,
wherein the third control transistor controls conduction and non-conduction between the vertical signal line and the pixel power supply line, and
the second potential is supplied to the pixel power supply line via the second control transistor and the third control transistor.

4. The solid-state imaging apparatus according to claim 1 ,
wherein a first metal line constituting the vertical signal line and a second metal line constituting the pixel power supply line are arranged parallel to each other, each of the first metal line and the second metal line being disposed in the pixel array unit.

5. The solid-state imaging apparatus according to claim 1 , further comprising:
a column readout circuit that is provided on each of a plurality of the vertical signal lines corresponding to a different one of a plurality of columns of the pixel array unit and converts an amount of the signal charges read out to the each of the plurality of the vertical signal lines from analog format to digital format; and
a fifth control transistor that controls conduction and non-conduction between the vertical signal line and the column readout circuit,
wherein, during a period in which at least the second control transistor and the third control transistor are ON, the fifth control transistor is OFF.

6. The solid-state imaging apparatus according to claim 1 ,
wherein the second potential is used as a controlled potential for turning ON the transfer transistor.

7. The solid-state imaging apparatus according to claim 1 ,
wherein a set of the constant current source transistor for supplying a constant current to the vertical signal line, the first control transistor for supplying the first potential to the vertical signal line, the second control transistor for supplying the second potential to the vertical signal line, and the third control transistor for supplying the second potential to the pixel power supply line is disposed at each of an upper end portion and a lower end portion of the pixel array unit.

8. A method for driving a solid-state imaging apparatus,
the solid-state imaging apparatus including:
a pixel array unit in which a plurality of pixel cells are arranged in a matrix, each of the plurality of the pixel cells including a photoelectric conversion element, a transfer transistor that transfers signal charges photoelectrically converted by the photoelectric conversion element to a floating diffusion, a reset transistor that resets the floating diffusion, and an amplifying transistor that outputs an amplified signal corresponding to an amount of the signal charges;
a vertical signal line that is connected to a source electrode of the amplifying transistor and receives an output of the amplifying transistor;
a pixel power supply line that is connected to a drain electrode of the amplifying transistor;
a first control transistor for supplying a first potential to the vertical signal line;
a second control transistor for supplying a second potential higher than the first potential to the vertical signal line; and
a third control transistor for supplying the second potential to the pixel power supply line,
the method comprising
turning ON the second control transistor and the third control transistor and applying the second potential to the vertical signal line and the pixel power supply line, during a period in which the transfer transistor is turned ON and transfers the signal charges to the floating diffusion.

9. An imaging apparatus comprising:
the solid-state imaging apparatus according to claim 1 that captures an image of a subject;
an imaging optical system that guides incident light from the subject to the solid-state imaging apparatus; and
a signal processing unit configured to process an output signal from the solid-state imaging apparatus.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Amikawa Hiroyuki
• Murakami Masashi

Classifications

• H04N25/709

  Circuitry for control of the power supply · CPC title

• H04N25/57 Primary

  Control of the dynamic range · CPC title

• H04N25/766

  comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/153 Primary

  Two-dimensional or three-dimensional array CCD image sensors · CPC title