Methods of forming serpentine thermal interface material and structures formed thereby

US9418912B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9418912-B2
Application numberUS-201514952651-A
CountryUS
Kind codeB2
Filing dateNov 25, 2015
Priority dateDec 21, 2012
Publication dateAug 16, 2016
Grant dateAug 16, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments.

First claim

Opening claim text (preview).

What is claimed is: 1. A package structure comprising: a first TIM structure comprising: a first interface material on a top surface of a device; a serpentine foil disposed on the first interface material, wherein the serpentine foil comprises a repeating serpentine pattern; a second interface material on the serpentine foil, wherein an apex portion of the serpentine foil is in contact with at least one of the first and second interface materials; and an integrated heat structure (IHS) disposed on the second interface material of the first TIM structure. 2. The structure of claim 1 wherein the device comprises one of a CPU die and a memory die. 3. The structure of claim 1 wherein the integrated heat structure comprises a heat sink. 4. The structure of claim 1 further comprising wherein the serpentine foil material comprises copper. 5. The structure of claim 1 further comprising a system comprising: a bus communicatively coupled to the package structure; and an eDRAM communicatively coupled to the bus. 6. The structure of claim 1 further comprising wherein the thermal conductivity of at least one of the first and second TIM structures comprises up to about 100 W/K-m. 7. The structure of claim 1 further comprising wherein a bottom portion of the device comprises a second TIM structure comprising: a first interface material; a serpentine foil disposed on the first interface material, wherein the serpentine foil comprises a repeating serpentine pattern; and a second interface material on the serpentine foil, wherein an apex portion of the serpentine foil is in contact with at least one of the first and second interface materials. 8. The structure of claim 7 further comprising wherein the second TIM structure is disposed on a top surface of a package substrate. 9. The structure of claim 7 further comprising wherein the first TIM comprises one of parallel TIM and a rotated TIM, and the second TIM comprises one of a parallel TIM and a rotated TIM. 10. A package structure comprising: a first TIM structure comprising: a first interface material on a top surface of a device; a serpentine foil disposed on the first interface material, wherein the serpentine foil comprises a repeating serpentine pattern; a second interface material on the serpentine foil, wherein an apex portion of the serpentine foil is in contact with and extends into at least one of the first and second interface materials; and an integrated heat structure (IHS) disposed on the second interface material of the first TIM structure. 11. The structure of claim 10 wherein the device comprises one of a CPU die and a memory die. 12. The structure of claim 10 wherein the integrated heat structure comprises a heat sink. 13. The structure of claim 10 further comprising wherein the serpentine foil material comprises copper. 14. The structure of claim 10 further comprising a system comprising: a bus communicatively coupled to the package structure; and an eDRAM communicatively coupled to the bus. 15. The structure of claim 10 further comprising wherein the thermal conductivity of at least one of the first and second TIM structures comprises up to about 100 W/K-m. 16. The structure of claim 10 further comprising wherein a bottom portion of the device comprises a second TIM structure comprising: a first interface material; a serpentine foil disposed on the first interface material, wherein the serpentine foil comprises a repeating serpentine pattern; and a second interface material on the serpentine foil, wherein an apex portion of the serpentine foil is in contact with and extends into at least one of the first and second interface materials. 17. The structure of claim 16 further comprising wherein the second TIM structure is disposed on a top surface of a package substrate. 18. The structure of claim 16 further comprising wherein the first TIM comprises one of parallel TIM and a rotated TIM, and the second TIM comprises one of a parallel TIM and a rotated TIM.

Assignees

Inventors

Classifications

  • the means being corrugated, plate-like elements · CPC title

  • on encapsulations · CPC title

  • On different surfaces · CPC title

  • Dispositions, e.g. layouts · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9418912B2 cover?
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments.
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W40/226. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).