Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates
US-9111927-B2 · Aug 18, 2015 · US
Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates
US9418906B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9418906-B2 |
| Application number | US-201514816611-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 3, 2015 |
| Priority date | Apr 6, 2009 |
| Publication date | Aug 16, 2016 |
| Grant date | Aug 16, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
First claim
Opening claim text (preview).
What is claimed is: 1. A method incorporating specialized pins, comprising: providing a system functional pin; providing a system functional pin depopulation zone; and positioning a non-system functional pin within the system functional pin depopulation zone, wherein the non-system functional pin sends test signals and a stacked-socket interposer probe head assembly is to receive a signal from the non-system functional pin, and passes the signal from the system functional pin to a socket. 2. The method of claim 1 , wherein the system functional pin depopulation zone is to be used to provide a mechanical seating between the package and a socket. 3. The method of claim 1 , wherein the non-system functional pin is an Input-Output pin, a debug pin, or a test pin. 4. The method of claim 1 , wherein the system functional pin depopulation zone is to be used to provide a mechanical seating between the package and a socket. 5. The method of claim 1 , wherein the system functional pin depopulation zone includes a plurality of functional pin depopulation zones. 6. The method of claim 1 , wherein the non-system functional pin includes a plurality of non-system functional pins. 7. The method of claim 1 , wherein the system functional pin and the non-system functional pin are located on a bottom side of a CPU.
Assignees
Inventors
Classifications
Interconnections for measuring or testing, e.g. probe pads · CPC title
Shapes or dispositions of interconnections · CPC title
characterised by the relative positions of pads or connectors relative to package parts · CPC title
- H10P74/207Primary
Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title
- H01L22/14Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9418906B2 cover?
- In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P74/207. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).