Integrated circuit with on-die decoupling capacitors

Patent metadata

Field	Value
Publication number	US-9418873-B2
Application number	US-201414467039-A
Country	US
Kind code	B2
Filing date	Aug 24, 2014
Priority date	Aug 24, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
an integrated circuit (IC) die including a processor having first and second interfaces, at least one decoupling capacitor, at least one capacitor pad connected to the decoupling capacitor, first and second internal connection pads connected respectively to the first and second interfaces, at least one intermediate connection pad, and a plurality of die bonding pads;
a package for the semiconductor die having electrical contacts for connection to external electrical circuitry;
a plurality of external connection members comprising first bond wires that connect respective die bonding pads with the package electrical contacts;
at least one internal connection member selectively connecting the decoupling capacitor by way of the first or the second internal connection pad and the capacitor pad for decoupling the first or the second interface respectively, and
wherein the internal connection member comprises second bond wires that respectively connect the intermediate connection pad to the capacitor pad, and the selected internal connection pad to the intermediate connection pad.

2. The semiconductor device of claim 1 , wherein the first and second interfaces have first and second power distribution lines respectively, and the first and second internal connection pads are connected to the first and second power distribution lines respectively.

3. The semiconductor device of claim 1 , wherein the second bond wires for the selected one of the first and the second interfaces operationally connect the die bonding pads with the package electrical contacts and the internal connection pads with the capacitor pad of the die, and leave floating die bonding pads and the internal connection pads of the other one of the first and the second interfaces.

4. A semiconductor integrated circuit (IC) die, comprising:
a processor including first and second interfaces;
die bonding pads for connection to external electrical contacts of a package for the die;
at least one decoupling capacitor;
at least one capacitor pad connected to the decoupling capacitor; and
first and second internal connection pads respectively connected to the first and second interfaces for connection by at least one internal connection member alternatively to the capacitor pad for decoupling the first or the second interface,
wherein:
the die bonding pads are connectable by first bond wires to the external contacts,
the internal connection pads are connectable by at least one second bond wire alternatively to the capacitor pad,
the IC die also includes at least one intermediate connection pad that is connectable by a third bond wire to the capacitor pad, and
the internal connection pads are connectable alternatively by the at least one second bond wire to the intermediate connection pad.

5. The semiconductor die of claim 4 , wherein the first and second interfaces have first and second power distribution lines respectively, and the first and second internal connection pads are connected to the first and second power distribution lines respectively.

Assignees

• Kumar Shailesh
• Garg Vikas
• Varshney Sumit
• Verma Chetan
• Freescale Semiconductor Inc

Inventors

• Kumar Shailesh
• Garg Vikas
• Varshney Sumit
• Verma Chetan

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title