Apparatus for boosting source-line voltage to reduce leakage in resistive memories

Patent metadata

Field	Value
Publication number	US-9418761-B2
Application number	US-201414569573-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.

First claim

We claim:

1. An apparatus comprising:
a leakage tracker to track leakage current of a column of resistive memory cells; and
a circuit, coupled to the leakage tracker, for adjusting voltage on a Source Line (SL) of the column of resistive memory cells.

2. The apparatus of claim 1 , wherein the circuit is to adaptively adjust the voltage on the SL.

3. The apparatus of claim 1 , wherein the leakage tracker includes a replica column of resistive memory cells, and wherein the replica column includes a Bit Line (BL) and a SL.

4. The apparatus of claim 3 , wherein the circuit includes a current mirror.

5. The apparatus of claim 4 , wherein the circuit includes a negative feedback path to control a voltage on a gate terminal of a transistor such that leakage current through the replica column is substantially equal to a ratio of current of the current mirror.

6. The apparatus of claim 3 , wherein the SL of the replica column is electrically shorted to a SL of a data column.

7. The apparatus of claim 3 , wherein at least one of the resistive memory cells includes an access transistor having a gate terminal coupled to ground, and wherein the access transistor includes a source/drain terminal coupled to the SL.

8. The apparatus of claim 1 , wherein the circuit is operable to turn on during memory read operations.

9. The apparatus of claim 1 , wherein the circuit is operable to turn off during non-read operations.

10. The apparatus of claim 1 , wherein the replica column is positioned within data columns of a memory array.

11. The apparatus of claim 1 , wherein the resistive memory cells comprise at least one of:
a magnetic tunneling junction device;
a phase change memory cell; or
a resistive random access memory.

12. The apparatus of claim 1 , wherein the leakage tracker comprises one or more transistors mimicking leakage behavior of a column of resistive memory cells.

13. The apparatus of claim 12 , wherein the one or more transistors are of same or different type than transistors of the circuit.

14. The apparatus of claim 1 , wherein the leakage tracker is structurally substantially identical to a data column.

15. The apparatus of claim 1 comprises a unity gain amplifier coupled to the circuit, wherein the unity gain amplifier is to generate a boosted SL voltage for the column of resistive memory cells.

16. An apparatus comprising:
a memory array having rows and columns of resistive memory cells;
a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and
a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a Source Line (SL) of the column of resistive memory cells during read operation.

17. The apparatus of claim 16 , wherein the leakage tracker includes a replica column of resistive memory cells, wherein the replica column has a Bit Line (BL) and a SL.

18. The apparatus of claim 16 , wherein the circuit includes a current mirror, and wherein the circuit includes a negative feedback path to control a voltage to a gate terminal of a transistor such that leakage current through the replica column is substantially equal to a ratio of current of the current mirror.

19. A system comprising:
a memory;
a processor coupled to the memory, the processor including an apparatus which comprises:
a leakage tracker to track leakage current of a column of resistive memory cells; and
a circuit, coupled to the leakage tracker, for adjusting voltage on a Source Line (SL) of the column of resistive memory cells; and

a wireless interface for allowing the processor to communicate with another device.

20. The system of claim 19 , wherein the leakage tracker includes a replica column of resistive memory cells, and wherein the replica column has a Bit Line (BL) and a SL.

21. The system of claim 19 , wherein the circuit includes:
a current mirror; and
a negative feedback path to control a voltage to a gate terminal of a transistor such that leakage current through the replica column is substantially equal to a ratio of current of the current mirror.

Assignees

• Intel Corp

Inventors

• Arslan Umut
• Dray Cyrille

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2029/5006

  Current · CPC title

• G11C29/08 Primary

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title