Memory devices and methods of operating the same

Patent metadata

Field	Value
Publication number	US-9418739-B2
Application number	US-201514616806-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Apr 4, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

First claim

What is claimed is:

1. A method of operating a memory device including memory cells disposed at respective intersections of bit lines and word lines, wherein each memory cell includes a variable resistor and a selection element, the method comprising:
during a first pre-charge mode, applying a pre-charge voltage to a selected bit line connected to a selected memory cell among the memory cells, non-selected bit lines, and a selected word line connected to the selected memory cell;
during a second pre-charge mode following the first pre-charge mode, reducing the pre-charge voltage applied to the non-selected bit lines to a first inhibition voltage; and
during an active mode following the second pre-charge mode, applying a first set write voltage greater than the pre-charge voltage to the selected bit line and reducing the pre-charge voltage applied to the selected word line to a voltage higher than the first inhibition voltage.

2. The method of claim 1 , further comprising:
applying a set write current to the selected word line.

3. The method of claim 2 , wherein when the first set write voltage is applied to the selected bit line and the set write current flows through the selected memory cell, a resistive state of the selected memory cell changes from a first resistive state to a second resistive state lower than the first resistive state, such that a first data value is stored in the selected memory cell.

4. The method of claim 3 , further comprising:
applying a second set write voltage higher than the first set write voltage to the selected bit line,
wherein when the second set write voltage is applied to the selected bit line and the voltage higher than the first inhibition voltage is applied to the selected word line, a resistive state of the selected memory cell changes from the second resistive state to a third resistive state lower than the second resistive state.

5. The method of claim 1 , further comprising:
applying a second inhibition voltage to non-selected word lines.

6. The method of claim 5 , wherein the second inhibition voltage is substantially equal to half of the first set write voltage.

7. The method of claim 1 , wherein the first inhibition voltage is substantially equal to a ground voltage.

8. The method of claim 1 , further comprising:
applying a reset write voltage to the selected word line;
applying a second voltage lower than the reset write voltage to the selected bit line;
applying a third inhibition voltage to the non-selected bit lines; and
applying a fourth inhibition voltage to non-selected word lines.

9. The method claim of claim 8 , wherein the third inhibition voltage is substantially equal to half of the reset write voltage, and the fourth inhibition voltage is substantially equal to ground voltage.

10. The method of claim 8 , wherein when the reset write voltage is applied to the selected word line and the second voltage is applied to the selected bit line, a resistive state of the selected memory cell changes from a first resistive state to a second resistive state higher than the first resistive state.

11. The method of claim 1 , further comprising:
applying a read voltage to the selected bit line; and
electrically connecting the selected word line to a sense amplification unit, wherein the sense amplification unit compares a voltage level of the selected word line with a reference voltage to read a data value stored in the selected memory cell.

12. The method of claim 11 , wherein a read current flows through the selected memory cell when the read voltage is applied to the selected bit line, and the read current flows to ground voltage through a read driver included in the sense amplification unit.

13. A method of operating a memory device including memory cells disposed at respective intersections of bit lines and word lines, wherein each memory cell includes a variable resistor and a selection element, the method comprising:
during a first pre-charge mode, applying a pre-charge voltage to a selected word line connected to a selected memory cell among the memory cells, non-selected word lines, and a selected bit line connected to the selected memory cell;
during a second pre-charge mode following the first pre-charge mode, reducing the pre-charge voltage applied to the non-selected word lines to a first inhibition voltage; and
during an active mode following the second pre-charge mode, applying a set write voltage greater than the pre-charge voltage to the selected word line and reducing the pre-charge voltage applied to the selected bit line to a voltage higher than the first inhibition voltage.

14. The method of claim 13 , further comprising:
applying a set current to the selected bit line.

15. The method of claim 14 , wherein when the set write voltage is applied to the selected word line and the set write current flows through the selected memory cell, a resistive state of the selected memory cell changes from a first resistive state to a second resistive state lower than the first resistive state, such that a first data value is stored in the selected memory cell.

16. The method of claim 13 , further comprising:
applying a second inhibition voltage to non-selected bit lines.

17. The method of claim 16 , wherein the second inhibition voltage is substantially equal to half of the set write voltage.

18. The method of claim 13 , wherein the first inhibition voltage is substantially equal to a ground voltage.

19. The method of claim 18 , wherein the pre-charge voltage is substantially equal to half of the set write voltage.

20. A method of operating a memory device including resistive memory cells disposed at respective intersections of bit lines and word lines, the method comprising:
during a set write operation, applying a set write voltage to a selected bit line, and connecting a write driver to a selected word line; and
during a reset write operation, applying a reset write voltage to the selected word line, and connecting the write driver to the selected bit line,
wherein the write driver provides a set current to the selected word line during the set write operation, and provides a reset current to the selected bit line during the reset write operation.

Assignees

• Lee Yong-Kyu
• Lee Yeong-Taek
• Samsung Electronics Co Ltd

Inventors

• Lee Yong-Kyu
• Lee Yeong-Taek

Classifications

• G11C2013/0071

  Write using write potential applied to access device gate · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title