Cycle-accurate replay and debugging of running FPGA systems

Patent metadata

Field	Value
Publication number	US-9418187-B2
Application number	US-201514940686-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 1, 2013
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible to recreate a cycle accurate execution of the hardware system in simulation. Unlike CHIPSCOPE and SIGNALTAP which let you monitor a small number of signals in the design, the tool provides visibility into the whole system.

First claim

What is claimed is:

1. A method for analyzing a hardware circuit implemented in a field-programmable gate array (FPGA), the method comprising:
receiving by a computer a log from the FPGA, the log indicating a plurality of events that occurred in the FPGA and respective timestamps associated with the events;
utilizing, by the computer, the log to replay a prior FPGA execution in a simulation, wherein the replay is based upon non-deterministic input data and timing information in the log, and wherein the replay is performed using a hardware description language (HDL) code which is the same as that used to configure the FPGA after synthesis; and
outputting, by the computer, the simulation.

2. The method of claim 1 , further comprising:
determining, by the FPGA, the plurality of events that occurred in the FPGA;
associating, by the FPGA, a timestamp with each of the determined events; and
creating, by the FPGA, the log of the events and respective timestamps.

3. The method of claim 1 , wherein the computer is a host computer.

4. The method of claim 3 , wherein the log is communicated to the host computer at a time selected from: (a) real-time, as a process progresses in the FPGA; (b) in a batch, after a process had completed in the FPGA; and (c) a combination thereof.

5. The method of claim 1 , wherein the replay of the prior FPGA execution in simulation is used for at least one of: (a) debugging; (b) performance analysis; and (c) a combination thereof.

6. The method of claim 1 , wherein a reproduction of the prior FPGA execution in simulation is a 100 percent clock cycle accurate reproduction.

7. The method of claim 1 , wherein the log during execution is stored in at least one of: (a) an internal memory of the FPGA; (b) a memory external to the FPGA; and (c) a combination thereof.

8. The method of claim 1 , wherein the simulation is output by the computer to a display.

9. A computer program product for analyzing a hardware circuit implemented in a field-programmable gate array (FPGA), the computer program product comprising:
a first computer readable storage medium having program instructions embodied therewith, the program instructions of the first computer readable storage medium executable at least in part by a computer to cause the computer to perform a method comprising:
receiving a log from the FPGA, the log indicating a plurality of events that occurred in the FPGA and respective timestamps associated with the events;
utilizing the log to replay a prior FPGA execution in a simulation, wherein the replay is based upon non-deterministic input data and timing information in the log, and wherein the replay is performed using a hardware description language (HDL) code which is the same as that used to configure the FPGA after synthesis; and
outputting the simulation.

10. The computer program product of claim 9 , further comprising a second computer readable storage medium having program instructions embodied therewith, the program instructions of the second computer readable storage medium executable at least in part by the FPGA to cause the FPGA to perform a method comprising:
determining the plurality of events that occurred in the FPGA;
associating a timestamp with each of the determined events; and
creating the log of the events and respective timestamps.

11. The computer program product of claim 9 , wherein the computer is a host computer.

12. The computer program product of claim 11 , wherein the log is communicated to the host computer at a time selected from: (a) real-time, as a process progresses in the FPGA; (b) in a batch, after a process had completed in the FPGA; and (c) a combination thereof.

13. The computer program product of claim 9 , wherein the replay of the prior FPGA execution in simulation is used for at least one of: (a) debugging; (b) performance analysis; and (c) a combination thereof.

14. The computer program product of claim 9 , wherein a reproduction of the prior FPGA execution in simulation is a 100 percent clock cycle accurate reproduction.

15. The computer program product of claim 9 , wherein the log during execution is stored in at least one of: (a) an internal memory of the FPGA; (b) a memory external to the FPGA; and (c) a combination thereof.

16. The computer program product of claim 9 , wherein the simulation is output by the computer to a display.

Assignees

• IBM

Inventors

• Foisy Daniel
• Shukla Sunil K

Classifications

• G06F30/23

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G01R31/318519 Primary

  Test of field programmable gate arrays [FPGA] · CPC title

• G06F17/5018

  Physics · mapped topic

• G06F17/5031 Primary

  Physics · mapped topic

• G06F30/343 Primary

  Logical level · CPC title