Integrated circuit with a high-speed debug access port

Patent metadata

Field	Value
Publication number	US-9255968-B2
Application number	US-201314087690-A
Country	US
Kind code	B2
Filing date	Nov 22, 2013
Priority date	Nov 22, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit.

First claim

What is claimed is:

1. An integrated circuit comprising:
high speed serial interface circuitry having a function circuit block that receives a data packet from external circuitry; and
a dedicated debug port in the high speed serial interface circuitry coupled to the function circuit block that transmits the received data packet to debug circuitry on the integrated circuit.

2. The integrated circuit defined in claim 1 , wherein the high speed serial interface circuitry comprises a peripheral component interconnect express (PCIe) interface.

3. The integrated circuit defined in claim 2 , wherein the function circuit block comprises a dedicated debug function circuit block in the PCIe interface, wherein the external circuitry comprises a root complex module, and wherein the dedicated debug function circuit block allows the root complex module to access the dedicated debug port.

4. The integrated circuit defined in claim 3 , wherein the data packet comprises debugging signals, and wherein the high speed serial interface circuitry further comprises:
a user function circuit block that receives a user data packet from the external circuitry; and
a user port in the high speed serial interface circuitry that transmits the received user data packet to user circuitry on the integrated circuit.

5. The integrated circuit defined in claim 1 further comprising:
a joint test action group (JTAG) circuit block coupled to the dedicated debug port, wherein the received data packet is transmitted from the dedicated debug port to the debug circuitry via the JTAG circuit block.

6. The integrated circuit defined in claim 1 , wherein the data packet comprises a debug data packet, and wherein the function circuit block comprises a user function circuit block that is adapted to receive one of the debug data packet and a user data packet, the integrated circuit further comprising:
arbitration logic circuitry coupled to the function circuit block, wherein the arbitration logic circuitry selectively transmits the user data packet to a user port in the high speed serial interface circuitry, and selectively transmits the debug data packet to the dedicated debug port.

7. The integrated circuit defined in claim 6 , further comprising:
a direct memory access (DMA) controller in the high speed serial interface circuitry; and
additional arbitration logic circuitry coupled to the dedicated debug port, wherein the additional arbitration logic circuitry receives the debug data packet at a first input and an output from the DMA controller, and wherein the additional arbitration logic circuitry selectively transmits one of the debug data packet and the output from the DMA controller to the dedicated debug port.

8. The integrated circuit defined in claim 6 , wherein the dedicated debug port comprises a master port, wherein the high speed serial interface circuitry further comprises a slave port, and wherein the arbitration logic circuitry selectively transmits a plurality of configuration instructions to the slave port.

9. The integrated circuit defined in claim 8 further comprising:
a direct memory access (DMA) controller that receives the plurality of configuration instructions from the slave port; and
additional arbitration logic circuitry that receives the debug data packet from the master port, and that receives an output from the DMA controller, and wherein the additional arbitration logic circuitry selectively transmits one of the debug data packet and the output from the DMA controller to the debug circuitry.

10. The integrated circuit defined in claim 1 , wherein the dedicated debug port comprises a memory mapped master port.

11. A method for providing debugging capability in an integrated circuit, the method comprising:
providing a dedicated debug port in a high speed serial interface circuit on the integrated circuit;
providing a function block to access the dedicated debug port in the high speed serial interface circuit; and
compiling a user design with debug circuitry to form a plurality of debugging paths from the debug circuitry in the user design to the dedicated debug port.

12. The method defined in claim 11 further comprising:
inserting the debug circuitry in the user design prior to compiling the user design.

13. The method defined in claim 11 , wherein the high speed serial interface circuit comprises a peripheral component interconnect express (PCIe) interface circuit that is adapted to receive user data packets and debugging signals, wherein the function block comprises a dedicated debug function block, and wherein the user design comprises a plurality of user application circuit blocks, the method further comprising:
providing a user port in the high speed serial interface circuit;
providing a user function to access the user port; and
forming a plurality of user signal paths from the user port to the plurality of user application circuit blocks when compiling the user design.

14. The method defined in claim 11 further comprising:
providing a direct memory access (DMA) controller in the high speed serial interface circuit to access the dedicated debugging port.

15. The method defined in claim 11 further comprising:
providing a user port in the high speed serial interface circuit; and
providing an arbitration logic circuit to selectively couple an output of the function block to one of the user port and the dedicated debug port.

16. A method of operating an integrated circuit, the method comprising:
receiving debugging signals from external circuitry at a dedicated debug function circuit block in a high speed serial interface circuit;
transmitting the debugging signals to a dedicated debug port in the high speed serial interface circuit; and
with the dedicated debug port in the high speed serial interface circuit, transmitting the debugging signals to debug circuitry in the integrated circuit.

17. The method defined in claim 16 , wherein the high speed serial interface circuit comprises a peripheral component interconnect express (PCIe) interface circuit, the method further comprising:
with the debugging circuitry, performing a debug operation on the integrated circuit using the debugging signals; and
with a user function circuit block in the PCIe interface circuit, receiving a data packet while performing the debug operation.

18. The method defined in claim 16 , wherein the dedicated debug port comprises a memory mapped master port, and wherein transmitting the debugging signals to the debug port comprises:
transmitting the debugging signals with a direct memory access (DMA) controller circuit in the high speed serial interface circuit.

19. The method defined in claim 18 further comprising:
configuring the DMA controller circuit prior to transmitting the debugging signals.

20. The method defined in claim 16 , wherein transmitting the debugging signals to debug circuitry in the integrated circuit comprises:
with the dedicated debug port, transmitting the debugging signals to a joint test action group (JTAG) circuit block coupled to the dedicated debug port; and
with the JTAG circuit block, transmitting the debugging signals to the debug circuitry.

Assignees

• Altera Corp

Inventors

• Finan Christopher D

Classifications

• G01R31/318519 Primary

  Test of field programmable gate arrays [FPGA] · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title