Methods and apparatus for multi-level cache hierarchies

Patent metadata

Field	Value
Publication number	US-9251070-B2
Application number	US-201213720549-A
Country	US
Kind code	B2
Filing date	Dec 19, 2012
Priority date	Dec 19, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A multi-level cache structure in accordance with one embodiment includes a first cache structure and a second cache structure. The second cache structure is hierarchically above the first cache. The second cache includes a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data. The selector array is configured to specify, for each corresponding tag entry, whether the data array includes the data corresponding to that tag entry.

First claim

What is claimed is:

1. A multi-level cache structure comprising:
a first cache structure;
a second cache structure, the second cache structure being hierarchically above the first cache; and
the second cache comprising a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data, wherein the tag array has an N-way associativity and the data array has M ways, where N and M are integers, with N being a larger integer than M;
wherein the selector array comprises a plurality of bits that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data corresponding to the tag entry is present in the data array, a position of the data corresponding to the tag entry in the data array.

2. The multi-level cache structure of claim 1 , further including a status array associated with the tag array, wherein a validity and status of the data corresponding to each tag entry is determined based on the status array.

3. The multi-level cache structure of claim 1 , wherein the plurality of bits that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data corresponding to the tag entry is present in the data array, a position of the data corresponding to the tag entry in the data array comprise:
a “data-valid” bit indicating whether or not data corresponding to the tag entry is present in the data array; and
one or more “way-selector” bits indicating the position of the data corresponding to the tag entry in the data array.

4. The multi-level cache structure of claim 1 , wherein the second cache structure is a level-2 cache.

5. The multi-level cache structure of claim 1 , wherein the second cache structure is inclusive with respect to the first cache structure.

6. The multi-level cache structure of claim 1 , wherein the second cache structure is a set-associative cache.

7. A cache structure comprising:
a tag array including a plurality of tag entries corresponding to respective addresses of data within a system memory;
a selector array associated with the tag array; and
a data array configured to store a subset of the data, wherein the tag array has an N-way associativity and the data array has M ways, where N and M are integers, with N being a larger integer than M;
wherein the selector array comprises a plurality of bits that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data corresponding to the tag entry is present in the data array, a position of the data corresponding to the tag entry in the data array.

8. The cache structure of claim 7 , further including a status array associated with the tag array, wherein the subset of a validity and status of the data corresponding to each tag entry is determined based on the status array.

9. The cache structure of claim 7 , wherein the plurality of bits in the selector array that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data is present in the data array, the position of the data in the data array comprise:
a “data-valid” bit indicating whether the data array includes the data corresponding to a tag entry; and
one or more “way-selector” bits indicating the position of the data corresponding to the tag entry in the data array.

10. The cache structure of claim 9 , wherein the cache structure is four-way set associative.

11. The cache structure of claim 7 , wherein the cache structure is a level-2 cache.

12. The cache structure of claim 7 , wherein the cache structure is inclusive with respect to a lower-level cache structure.

13. The cache structure of claim 7 , wherein the cache structure is a set-associative cache.

14. A method for caching system memory data, comprising:
storing a subset of the system memory data within a data array of a second cache structure, the second cache structure hierarchically above a first cache structure and comprising a tag array including a plurality of tag entries corresponding to respective addresses of data within the system memory; and a selector array associated with the tag array, wherein the tag array has an N-way associativity and the data array has M ways, where N and M are integers, with N being a larger integer than M; and
indicating that the data array includes the subset of the system memory using the selector array and that tag array, wherein the indicating comprises setting, to corresponding values, some or all of a plurality of bits that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data corresponding to the tag entry is present in the data array, a position of the data corresponding to the tag entry in the data array.

15. The method of claim 14 , further including a status array associated with the tag array, wherein a validity and status of the data corresponding to each tag entry is determined based on the status array.

16. The method of claim 14 , wherein the plurality of bits that indicate, for each corresponding tag entry, whether or not data corresponding to the tag entry is present in the data array, and, when the data corresponding to the tag entry is present in the data array, a position of the data corresponding to the tag entry in the data array comprise:
a “data-valid” bit indicating whether the data array includes the data corresponding to a tag entry; and
one or more “way-selector” bits indicating the position of the data corresponding to the tag entry in the data array.

17. The method of claim 14 , wherein the second cache structure is inclusive with respect to the first cache structure.

18. The method of claim 14 , wherein the second cache structure is a set-associative cache.

Assignees

• Advanced Micro Devices Inc

Inventors

• Cho Jin Haeng

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title