Adaptive mapping of logical addresses to memory devices in solid state drives

Patent metadata

Field	Value
Publication number	US-9417803-B2
Application number	US-201213535889-A
Country	US
Kind code	B2
Filing date	Jun 28, 2012
Priority date	Sep 20, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A method for data storage includes receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units. Respective estimates of a performance characteristic are obtained for the multiple memory units. A mapping, which maps the logical addresses to respective physical storage locations in the multiple memory units, is adapted based on the estimates so as to balance the performance characteristic across the memory units. The data items are stored in the physical storage locations in accordance with the adapted mapping.

First claim

The invention claimed is:

1. A method for data storage, comprising:
receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units;
obtaining respective estimates of performance characteristics for the multiple memory units, wherein the performance characteristics for each memory unit include an indication of a respective count of memory blocks in the memory unit that are available for programming and further include a respective time duration of a memory access command applied to each memory unit;
based on the estimates, adapting, by a processor, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, thereby balancing the performance characteristics across the memory units, wherein balancing the performance characteristics includes writing frequently accessed data to faster memory units and rarely accessed data to slower memory units as determined by the respective time duration of memory access commands applied to each memory unit; and
storing the data items in the physical storage locations in accordance with the adapted mapping, wherein storing the data items comprises distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units, and wherein adapting the mapping comprises modifying one or more of the weights, wherein modifying the weights comprises assigning, to a given memory unit, different first and second weights for respective different first and second types of memory access commands, the types of memory access commands including read, write, and erase commands.

2. The method according to claim 1 , wherein adapting the mapping comprises modifying a total number of the logical addresses that are mapped to a given memory unit.

3. The method according to claim 1 , wherein obtaining the estimates comprises evaluating the performance characteristic for the multiple memory units during production of the memory or the memory units.

4. The method according to claim 1 , wherein obtaining the estimates comprises evaluating the performance characteristic for the multiple memory units while the memory is operating in a host system.

5. The method according to claim 1 , wherein adapting the mapping comprises initially storing the data items in the memory in accordance with an initial setting of the mapping, and subsequently adapting the mapping and copying one or more of the data items so as to store the data items in the memory in accordance with the adapted mapping.

6. The method according to claim 1 , wherein the performance characteristics for each memory unit include indications of a respective count of faulty memory blocks in that memory unit.

7. The method according to claim 1 , wherein the performance characteristics for each memory unit include an indication of a respective read error performance of that memory unit.

8. The method according to claim 1 , wherein the performance characteristics for each memory unit include an indication of a respective endurance of that memory unit.

9. The method according to claim 1 , wherein the performance characteristics for each memory unit include an indication of a respective frequency of access to data stored in each memory unit.

10. The method according to claim 1 , wherein the performance characteristics for each memory unit include an indication of a respective count of memory access commands pending for execution in that memory unit.

11. A data storage apparatus, comprising:
a memory interface configured to communicate with a memory that includes multiple memory units; and
a processor coupled to the interface and configured to:
receive data items associated with respective logical addresses for storage in the memory;
obtain respective estimates of performance characteristics for the multiple memory units, wherein the performance characteristics for each memory unit include an indication of a respective count of memory blocks in the memory unit that are available for programming and further include a respective time duration of a memory access command applied to each memory unit;
adapt, based on the estimates, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, thereby balancing the performance characteristics across the memory units, wherein balancing the performance characteristics includes writing frequently accessed data to faster memory units and rarely accessed data to slower memory units as determined by the respective time duration of memory access commands applied to each memory unit; and
store the data items in the physical storage locations in accordance with the adapted mapping, wherein storing the data items comprises the processor distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units and adapting the mapping by modifying one or more of the weights, wherein the processor is configured to assign, to a given memory unit, different first and second weights for respective different first and second types of memory access commands, the types of memory access commands including read, write, and erase commands.

12. The apparatus according to claim 11 , wherein the processor is configured to adapt the mapping by modifying a total number of the logical addresses that are mapped to a given memory unit.

13. The apparatus according to claim 11 , wherein the processor is configured to accept an evaluation of the performance characteristic for the multiple memory units, which was performed during production of the memory or the memory units.

14. The apparatus according to claim 11 , wherein the processor is configured to evaluate the performance characteristic for the multiple memory units while the memory is operating in a host system.

15. The apparatus according to claim 11 , wherein the processor is configured to initially store the data items in the memory in accordance with an initial setting of the mapping, and to subsequently adapt the mapping and copy one or more of the data items so as to store the data items in the memory in accordance with the adapted mapping.

16. The apparatus according to claim 11 , wherein the performance characteristics for each memory unit include indications of a respective count of faulty memory blocks in that memory unit.

17. The apparatus according to claim 11 , wherein the performance characteristics for each memory unit include an indication of a respective read error performance of that memory unit.

18. The apparatus according to claim 11 , wherein the performance characteristics for each memory unit are indicative of a respective endurance of that memory unit.

19. The apparatus according to claim 11 , wherein the performance characteristics for each memory unit include an indication of a respective frequency of access to data stored in that memory unit.

20. The apparatus according to claim 11 , wherein the performance characteristics for each memory unit include an indication of a respective count of memory access commands pending for execution in that memory unit.

21. A data storage apparatus, comprising:
a memory comprising multiple memory units; and
a processor coupled to the memory via a memory interface and configured to:
receive data items associated with respective logical addresses for storage in the memory;
obtain r

Assignees

• Sandel Eran
• Golov Oren
• Apple Inc

Inventors

• Sandel Eran
• Golov Oren

Classifications

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/3485

  for I/O devices · CPC title

• G06F11/008

  Reliability or availability analysis · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title