Limiting activity rates that impact life of a data storage media

Patent metadata

Field	Value
Publication number	US-8954689-B2
Application number	US-201113173935-A
Country	US
Kind code	B2
Filing date	Jun 30, 2011
Priority date	Jun 30, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A first cumulative data transfer over a first time window from an intermediary module to a data storage media is determined. The intermediary module is coupled between a host interface and the data storage media. An activity rate from the intermediary module to the data storage media is limited for one or more subsequent time windows if the first cumulative activity rate exceeds a threshold value that impacts life of the data storage media. The limitation of the activity rate is removed after the one or more subsequent time windows expire.

First claim

What is claimed is:

1. A method comprising:
determining a first cumulative rate of input/output operations over a first time window between an intermediary module and a solid-state, non-volatile memory, wherein the intermediary module is coupled between a host interface and the solid-state, non-volatile memory;
limiting a number of memory dies of the solid-state, non-volatile memory that may be simultaneously accessed to limit a subsequent rate of the input/output operations between the intermediary module and the solid-state, non-volatile memory for one or more subsequent time windows if the first cumulative rate exceeds a threshold value that impacts life of the solid-state, non-volatile memory; and
removing the limitation of the subsequent rate after the one or more subsequent time windows expire.

2. The method of claim 1 , further comprising adjusting a period of at least one of the first and subsequent time windows based on a historical pattern of activity between the intermediary module and the solid-state, non-volatile memory.

3. The method of claim 1 , wherein input/output rates between the intermediary module and the solid-state, non-volatile memory differ from input/output rates between the host interface and the intermediary module based on at least one of write amplification, compressibility of the data, random/sequential nature of the input/output, data size associated with the input/output, and historical patterns associated with the input/output.

4. The method of claim 1 , further comprising adjusting at least one of the threshold value and a value of the limitation placed on the subsequent rates based on a current level of wear associated with the solid-state, non-volatile memory and further in view of a current time in use of the solid-state, non-volatile memory.

5. The method of claim 1 , wherein, if one of a predetermined wear level threshold and a predetermined time in use is not yet reached, the subsequent rate is not limited if the first cumulative rate exceeds the threshold value.

6. The method of claim 1 , wherein the first cumulative rate of the input/output operations comprises a system-dependent, maximum, data transfer rate of the solid-state, non-volatile memory.

7. The method of claim 1 , wherein the input/output operations comprise a weighted combination of input/output operations per second of at least two of read, write, and erase operations.

8. An apparatus comprising:
an intermediary module coupled between a host interface and a solid-state, non-volatile memory; and
at least one controller that causes the apparatus to:
determine a cumulative rate of input/output operations between the intermediary module and the solid-state, non-volatile memory over a first time window;
limit a number of memory dies of the solid-state, non-volatile memory that may be simultaneously accessed to limit a subsequent rate of the input/output operations between the intermediary module and the solid-state, non-volatile memory for one or more subsequent time windows if the cumulative rate exceeds a threshold value that impacts life of the solid-state, non-volatile memory; and
remove the limitation of the subsequent rate after the one or more subsequent time windows expire.

9. The apparatus of claim 8 , wherein the controller further causes the apparatus to adjust at least one of the first and second time periods based on a historical pattern of activity between the intermediary module and the solid-state, non-volatile memory.

10. The apparatus of claim 8 , wherein activity rates between the intermediary module and the solid-state, non-volatile memory differ from activity rates between the host interface and the intermediary module based on at least one of write amplification, compressibility of the data, and random/sequential nature of the data transfer.

11. The apparatus of claim 8 , wherein the controller further causes the apparatus to adjust at least one of the threshold value and a value of the limitation placed on the subsequent rates based on a current level of wear associated with the solid-state, non-volatile memory in view of a current time in use of the data storage media.

12. The apparatus of claim 8 , wherein, if one of a predetermined wear level threshold and a predetermined time in use is not yet reached, the subsequent rate is not limited if the cumulative rate of the input/output operations exceeds the threshold value.

13. The apparatus of claim 8 , wherein the cumulative rate of the input/output operations comprises a system-dependent, maximum, data transfer rate of the solid-state, non-volatile memory.

14. The apparatus of claim 8 , wherein the input/output operations comprise a weighted combination of input/output operations per second of at least two of read, write, and erase operations.

Assignees

• Seekins David Scott
• Goss Ryan James
• Conklin Kristofer Carlson
• Seagate Technology Llc

Inventors

• Seekins David Scott
• Goss Ryan James
• Conklin Kristofer Carlson

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/1036

  Life time enhancement · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title