System and method of manufacturing a fin field-effect transistor having multiple fin heights

Patent metadata

Field	Value
Publication number	US-9412818-B2
Application number	US-201314100489-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Dec 9, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.

First claim

What is claimed is:

1. An apparatus comprising:
a first fin field effect transistor (FinFET) device having an aspect ratio of at least 3 and extending from a surface of a first etch stop layer, the first FinFET device including a first fin comprising a first fin layer, a second fin layer on the first etch stop layer, and an intermediate layer between the first fin layer and the second fin layer, wherein the first fin layer and the second fin layer comprise a first compound material, and wherein the intermediate layer comprises a second compound material comprising a II-VI or III-V compound material; and
a second FinFET device having an aspect ratio of less than 3 and extending from a surface of a second etch stop layer that is separated from the first etch stop layer by a compound layer.

2. The apparatus of claim 1 , wherein:
the first FinFET device further includes:
a first metal gate; and

a first oxide layer in contact with the first fin layer, the second fm layer, and the intermediate layer; wherein the second FinFET device includes:
a second metal gate;
a second oxide layer; and
a second fin in contact with the second oxide layer, wherein the second fin comprises the first compound material, and wherein the second etch stop layer comprises the second compound material.

3. The apparatus of claim 2 , wherein the first FinFET device has a first fin height defined by the first fin layer and the second fin layer, wherein the second FinFET device has a second fin height defined by the second fin, and wherein the first fin height is different than the second fin height.

4. The apparatus of claim 1 , wherein the first etch stop layer and the second etch stop layer comprise the second compound material.

5. The apparatus of claim 1 , wherein the intermediate layer comprises a first III-V compound, and wherein the first fin layer and the second fin layer comprise a second III-V compound that has a lower band gap energy than the first III-V compound.

6. The apparatus of claim 5 , wherein the first III-V compound includes aluminum arsenide, and wherein the second III-V compound includes gallium arsenide.

7. The apparatus of claim 5 , wherein the first III-V compound includes indium aluminum arsenide, and wherein the second III-V compound includes indium gallium arsenide.

8. The apparatus of claim 1 , wherein the intermediate layer comprises a first II-VI compound, and wherein the first fin layer and the second fin layer comprise a second II-VI compound that has lower band gap energy than the first II-VI compound.

9. The apparatus of claim 8 , wherein the first II-VI compound includes Zinc telluride (ZnTe), and wherein the second II-VI compound includes Cadmium telluride (CdTe).

10. The apparatus of claim 1 , wherein the second compound material has a higher band gap energy than the first compound material.

11. The apparatus of claim 1 , wherein the intermediate layer and the second etch stop layer comprise the second compound material.

12. The apparatus of claim 1 , wherein the compound layer comprises the first compound material.

13. The apparatus of claim 1 , wherein the first etch stop layer and the second etch stop layer are aluminum arsenide layers that control respective effective fin heights of the first FinFET and the second FinFET.

14. A method of forming a semiconductor device, the method comprising:
forming a first fin field effect transistor (FinFET) device having an aspect ratio of at least 3 that extends from a surface of a first etch stop layer, the first FinFET device including a first fin comprising a first fin layer, a second fin layer on the first etch stop layer, and an intermediate layer between the first fin layer and the second fin layer, wherein the first fin layer and the second fin layer comprise a first compound material, and wherein the intermediate layer comprises a second compound material comprising a II-VI or III-V compound material; and
forming a second FinFET device having an aspect ratio of less than 3 that extends from a surface of a second etch stop layer that is separated from the first etch stop layer by a first compound layer.

15. The method of claim 14 , further comprising:
forming the first etch stop layer on a surface of a substrate;
forming the first compound layer on the surface of the first etch stop layer;
forming the second etch stop layer on a surface of the first compound layer; and
forming a second compound layer on a surface of the second etch stop layer.

16. The method of claim 15 , further comprising:
patterning the second compound layer to form the first fin layer of the first fin of the first FinFET device and to form a second fin of the second FinFET device;
patterning the second etch stop layer to form the intermediate layer of the first fin; and
patterning the first compound layer to form the second fin layer of the first fin.

17. The method of claim 16 , wherein the first FinFET device includes:
a first metal gate; and
a first oxide layer in contact with the first fin layer, the second fin layer, and the intermediate layer;
wherein the second FinFET device includes:
a second metal gate;
a second oxide layer; and
the second fin in contact with the second oxide layer, wherein the second fin comprises the first compound material, and wherein the second etch stop layer comprises the second compound material.

18. The method of claim 17 , wherein the first FinFET device has a first fin height defined by the first fin layer and the second fin layer, and wherein the second FinFET device has a second fin height defined by the second fin.

19. The method of claim 18 , wherein the first fin height is different than the second fin height.

20. The method of claim 14 , wherein the first etch stop layer and the second etch stop layer are formed using the same material.

21. The method of claim 14 , wherein the intermediate layer is formed using a first III-V compound, and wherein the first fin layer and the second fin layer are formed using a second III-V compound that has a lower band gap energy than the first III-V compound.

22. The method of claim 21 , wherein the first III-V compound includes aluminum arsenide, and wherein the second III-V compound includes gallium arsenide.

23. The method of claim 14 , wherein the intermediate layer is formed using a first II-VI compound, and wherein the first fin layer and the second fm layer are formed using a second II-VI compound that has lower band gap energy than the first II-VI compound.

24. The method of claim 23 , wherein the first II-VI compound includes Zinc telluride (ZnTe) and wherein the second II-VI compound includes Cadmium telluride (CdTe).

25. An apparatus comprising:
a substrate; and
a fin-type semiconductor device extending from the substrate, the fm-type semiconductor device comprising:
means for providing a first fin-type conduction channel, the means for providing a first fin-type conduction channel comprising a first fin field effect transistor (FinFET) device having an aspect ratio of at least 3 and extending from a surface of a first etch stop layer, the first FinFET device including a first fin comprising a first fin layer, a second fin layer on the first etch stop layer, and an intermediate layer between the first fin layer and the second fin layer, wherein the first fin layer and the second fin layer comprise a first compound material, and wherein the intermediate layer comprises a sec

Assignees

• Qualcomm Inc

Inventors

• Yang Bin
• Li Xia
• Chidambaram Pr
• Yeap Choh Fei

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158 Primary

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10D62/86

  being Group II-VI materials, e.g. ZnO · CPC title