Transistor, method of manufacturing the transistor, and electronic device including the transistor

Patent metadata

Field	Value
Publication number	US-9412769-B2
Application number	US-201414450913-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Aug 5, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Example embodiments relate to a transistor, a method of manufacturing a transistor, and/or an electronic device including the transistor. In example embodiments, the transistor includes a first field effect transistor (FET) and a second FET connected in series to each other, wherein a first gate insulating film of the first FET and a second gate insulating film of the second FET have different leakage current characteristics or gate electric field characteristics.

First claim

What is claimed is:

1. A transistor comprising:
a first field effect transistor (FET) including a first gate electrode, a first gate insulating film, a channel layer, a drain electrode contacting a first portion of the channel layer, and an intermediate electrode contacting a second portion of the channel layer;
a second FET connected in series to the first FET, the second FET including a second gate electrode, a second gate insulating film, the channel layer, the intermediate electrode and a source electrode contacting a third portion of the channel layer;
wherein the first and second gate insulating films have one of different leakage current characteristics and different gate electric field characteristics.

2. The transistor of claim 1 , wherein the first gate insulating film is configured to generate a larger leakage current than the second gate insulating film.

3. The transistor of claim 2 , wherein an insulating property of the first gate insulating film is a lower than an insulating property of the second gate insulating film.

4. The transistor of claim 2 , wherein a porosity of the first gate insulating film is a higher than a porosity of the second gate insulating film.

5. The transistor of claim 2 , wherein the second gate insulating film of the second FET is configured to compensate for an off current increase due to a leakage current of the first FET.

6. The transistor of claim 2 , wherein the first gate insulating film is formed at a lower temperature than the second gate insulating film.

7. The transistor of claim 1 , wherein the first gate insulating film is configured to provide a lower gate electric field than the second gate insulating film.

8. The transistor of claim 7 , wherein a gate capacitance of the first FET is lower than a gate capacitance of the second FET.

9. The transistor of claim 7 , wherein a thickness of the first gate insulating film is thicker than a thickness of the second gate insulating film.

10. The transistor of claim 7 , wherein a dielectric constant of the first gate insulating film is lower than a dielectric constant of the second gate insulating film.

11. The transistor of claim 7 , wherein the second gate insulating film of the second FET is configured to compensate for a threshold voltage decrease and a subthreshold slope decrease due to the first gate insulating film.

12. The transistor of claim 11 , wherein a thickness of the second gate insulating film is thinner than a thickness of the first gate insulating film.

13. The transistor of claim 11 , wherein a dielectric constant of the second gate insulating film is higher than a dielectric constant of the first gate insulating film.

14. The transistor of claim 1 , wherein
one of the first FET and the second FET has a top gate structure, and
an other of the first FET and the second FET has a bottom gate structure.

15. The transistor of claim 14 , wherein
the first FET has a top gate structure, and
the second FET has a bottom gate structure.

16. An electronic device comprising:
the transistor of claim 1 .

17. The electronic device of claim 16 , wherein
the electronic device is a display device; and
the transistor is one of driving device and a switching device in the electronic device.

18. A transistor comprising:
a bottom gate electrode;
an insulating layer covering the bottom gate electrode;
a channel layer on the insulating layer;
a protection layer on the channel layer, the protection layer patterned to expose a plurality of regions spaced apart from each other on the channel layer;
a drain electrode and a source electrode respectively contacting both end regions among the plurality of regions of the channel layer;
an intermediate electrode contacting an intermediate region among the plurality of regions of the channel layer; and
a top gate electrode on the protection layer between the drain electrode and the intermediate electrode,
wherein the insulating layer and the protection layer respectively function as gate insulating films having one of different leakage current characteristics and gate electric field characteristics with respect to the bottom gate electrode and the top gate electrode.

19. The transistor of claim 18 , wherein an insulating property of the protection layer is lower than an insulating property of the insulating layer.

20. The transistor of claim 18 , wherein the protection layer comprises:
a first protection layer contacting the channel layer; and
a second protection layer covering the first protection layer, the source electrode, the intermediate electrode, and the drain electrode.

21. The transistor of claim 18 , wherein a thickness of the protection layer is thicker than a thickness of the insulating layer.

22. The transistor of claim 18 , wherein a dielectric constant of the protection layer is lower than a dielectric constant of the insulating layer.

23. The transistor of claim 18 , wherein the channel layer includes one of amorphous silicon, crystalline silicon, semiconductor oxide, and semiconductor nitride.

24. The transistor of claim 23 , wherein the semiconductor oxide includes at least one of In 2 O 3 , Ga 2 O 3 , ZnO, TiO 2 , Ta 2 O 3 , ZrO 2 , HfO 2 , and SnO 2 .

25. The transistor of claim 23 , wherein the semiconductor nitride includes one of Zn 3 N 2 -containing ZnON, ZnONF, Ga—ZnON, In—ZnON, Al—ZnON, Ga—ZnONF, In—ZnONF, and Al—ZnONF.

26. The transistor of claim 23 , wherein the top gate electrode includes a transparent electrode material.

27. An organic light-emitting display device comprising:
the transistor of claim 18 ;
a pixel electrode connected to the drain electrode of the transistor;
a common electrode on the pixel electrode; and
an organic emission layer between the pixel electrode and the common electrode.

28. A liquid crystal display device comprising:
the transistor of claim 18 ;
a pixel electrode connected to the drain electrode of the transistor;
a common electrode on from the pixel electrode; and
a liquid crystal layer between the pixel electrode and the common electrode.

29. A method of manufacturing a transistor, comprising:
forming an insulating layer covering a bottom gate electrode;
forming a channel layer on the insulating layer;
forming a protection layer on the channel layer, the protection layer being patterned to expose a plurality of regions spaced apart from each other on the channel layer,
the protection layer being formed under different deposition conditions than the insulating layer, and
the protection layer and the insulating layer having different leakage current characteristics;

forming a drain electrode, an intermediate electrode, and a source electrode respectively contacting the plurality of regions; and
forming a top gate electrode on the protection layer between the drain electrode and the intermediate electrode, wherein
the insulating layer and the protection layer respectively function as gate insulating films having one of different leakage current characteristics and gate electric field characteristics with respect to the bottom gate electrode and the top gate electrode.

30. The method of claim 29 , wherein the forming of the protection layer includes:
forming a first protection layer contacting the channel layer; and
forming a second protection layer to cover the first prot

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Kyoung-Seok
• Kim Sun-Jae
• Kim Tae-Sang

Classifications

• G02F1/13624 Primary

  having more than one switching element per pixel · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D44/456

  Structures for regeneration, refreshing or leakage compensation · CPC title

• H10D64/511

  for IGFETs · CPC title