Three-dimensional integrated circuit device fabrication including wafer scale membrane

Patent metadata

Field	Value
Publication number	US-9412620-B2
Application number	US-201514597327-A
Country	US
Kind code	B2
Filing date	Jan 15, 2015
Priority date	Jul 14, 2008
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

First claim

The invention claimed is:

1. A method for fabricating three-dimensional integrated circuits, the method comprising:
etching crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a donor wafer membrane comprising a device layer of the donor semiconductor wafer and a buried insulating layer, to remove at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface; and
supporting the donor semiconductor wafer with a supporting structure, the supporting structure allowing the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching
wherein the method further comprises:
before the etching, coating the device layer of the donor semiconductor wafer with a first polymer film that is resistant to etching chemistries.

2. The method of claim 1 , wherein the area comprises substantially an entire side of the substrate side, and wherein the supporting structure comprises a separate supporting structure attached to the donor semiconductor wafer prior to the etching.

3. The method of claim 2 , wherein the supporting structure comprises a plurality of additional support partitions that form a grid structure, the grid structure being aligned with edges of die across the donor semiconductor wafer.

4. A method for fabricating three-dimensional integrated circuits, the method comprising:
etching crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a donor wafer membrane comprising a device layer of the donor semiconductor wafer and a buried insulating layer, to remove at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface;
supporting the donor semiconductor wafer with a supporting structure, the supporting structure allowing the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching;
wherein, the method further comprises:
before the etching, coating the device layer of the donor semiconductor wafer with a first polymer film that is resistant to etching chemistries;
exposing the substrate side to an oxidizing plasma to create a continuous native silicon dioxide film on a surface of the substrate side that is opposite the device layer; and
defining the area by coating portions of the substrate side outside the area with a second polymer film that is resistant to etching chemistries, and
wherein the etching comprises:
etching the substrate side with a plasma etch tool to substantially thin the crystalline substrate to within a pre-determined thickness; and
exposing the substrate side to TMAH to etch silicon portions of the substrate side and not etch silicon dioxide portions of the substrate side, and
wherein the supporting structure comprises portions of the substrate side that are outside of the area and that are not etched by the etching.

5. The method of claim 4 , wherein the plasma etch tool comprises a clamping ring that protects at least a part of the substrate side that is outside of the area.

6. The method of claim 5 ,
wherein the area comprises a surface of the substrate side that is within an annular ring with a predefined width at an outer edge of the substrate side, and
wherein the clamping ring protects the annular ring.

7. The method of claim 4 , wherein the area comprises a surface of the substrate side that is within an annular ring having a predefined width at an outer edge of the substrate side.

8. The method of claim 7 ,
wherein the donor semiconductor wafer comprises, adjacent to an inner surface of the crystalline substrate, an insulating layer, and
wherein the etching removes all of the crystalline substrate within the area so as to expose the insulating layer.

9. The method of claim 7 , wherein the area is further defined to exclude at least one additional support partition within the annular ring.

10. The method of claim 9 , wherein the at least one additional support partition comprises a plurality of additional support partitions that form a grid structure, the grid structure being aligned with edges of die across the donor semiconductor wafer.

11. A method for fabricating three-dimensional integrated circuits, the method comprising:
etching crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a donor wafer membrane comprising a device layer of the donor semiconductor wafer and a buried insulating layer, to remove at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface;
supporting the donor semiconductor wafer with a supporting structure, the supporting structure allowing the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching; and
bonding at least a portion of the device layer of the donor semiconductor wafer to the acceptor surface of an acceptor semiconductor wafer such that flexing of the donor semiconductor wafer conforms the device layer of the donor semiconductor wafer to the acceptor surface of the acceptor semiconductor wafer.

12. The method of claim 11 ,
wherein the supporting structure comprises a plurality of additional support partitions that form a grid structure defining a plurality of cavities, the grid structure being aligned with edges of die across the donor semiconductor wafer and each cavity within the plurality of cavities circumscribing at least one die on the donor semiconductor wafer,
the method further comprising positioning, after the etching and the supporting, the device layer of the donor semiconductor wafer in proximity to and removed from the acceptor surface of the acceptor semiconductor wafer, the positioning causing at least one die on the donor semiconductor wafer to be aligned with a corresponding at least one die on the acceptor surface, and
wherein the bonding comprises adjusting a pressure within at least one cavity of the plurality of cavities to urge the at least one die circumscribed by at least one cavity into contact with the acceptor surface of the acceptor semiconductor wafer.

13. The method of claim 11 , further comprising:
positioning, after the etching and the supporting, the device layer of the donor semiconductor wafer in proximity to and removed from the acceptor surface of the acceptor surface, the positioning causing at least one die on the donor semiconductor wafer to be aligned with a corresponding at least one die on the acceptor surface, and
wherein the bonding comprises adjusting an internal pressure on a backside of the donor semiconductor wafer to urge the device layer of the donor semiconductor wafer into contact with the acceptor surface of the acceptor semiconductor wafer, wherein the backside is opposite the device layer of the donor wafer membrane.

14. The method of claim 13 ,
wherein the etching compr

Assignees

• Globalfoundries Us 2 Llc
• Globalfoundries Inc

Inventors

• La Tulipe Jr Douglas C
• Purushothaman Sampath
• Vichiconti James

Classifications

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10P72/7438

  with parts of the auxiliary support remaining in the finished device · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P90/00 Primary

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title