Edge rounded field effect transistors and methods of manufacturing

Patent metadata

Field	Value
Publication number	US-9412598-B2
Application number	US-97375610-A
Country	US
Kind code	B2
Filing date	Dec 20, 2010
Priority date	Dec 20, 2010
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.

First claim

What is claimed is:

1. A method comprising:
forming a tunneling dielectric region on a substrate;
forming a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region by depositing a nitride or silicon rich nitride layer, forming an oxide layer on the nitride or silicon rich nitride layer, etching back the oxide layer and a portion of the nitride or silicon rich nitride layer, and then oxidizing a portion of the remaining nitride or silicon rich nitride layer to form an oxynitride or silicon oxynitride layer on a final nitride or silicon rich nitride layer;
nitridating a surface of the blocking dielectric region;
forming a gate region on the nitridated blocking dielectric region; and
oxidizing the gate region to form a sidewall dielectric layer, wherein edge encroachment of the gate region during oxidizing the gate region to form the sidewall dielectric layer is suppressed by the nitridated blocking dielectric region.

2. The method according to claim 1 , further comprising oxidizing the charge trapping region along with the gate region.

3. The method according to claim 1 , wherein nitridating the surface of the blocking dielectric region comprises exposing the surface of the blocking dielectric region to nitrogen in a furnace anneal.

Assignees

• Fang Shenqing
• Chen Tung-Sheng
• Cypress Semiconductor Corp

Inventors

• Fang Shenqing
• Chen Tung-Sheng

Classifications

• H10D64/01344 Primary

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L27/11568

  Electricity · mapped topic