Method for fabricating NMOS and PMOS transistors on a substrate of the SOI, in particular FDSOI, type and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-9412589-B2
Application number	US-201414501639-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Oct 23, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

First claim

The invention claimed is:

1. A method for forming at least one NMOS transistor and at least one PMOS transistor, respectively, on different regions of a silicon-on-insulator (SOI) substrate, comprising:
forming a first gate region on a first region of the SOI substrate, and a second gate region on a second region of the SOI substrate;
forming a first lateral insulating layer on sidewalls of the first and second gate regions;
forming on the first and second regions of the SOI substrate a respective pair of first faceted semiconductor blocks of a first semiconductor material adjacent the first lateral insulating layers, with a gap being formed between an inclined profile of each first faceted semiconductor block and a corresponding first lateral insulating layer, the first semiconductor material having a first type of conductivity for a first type of transistor;
forming second and third lateral insulating layers on sidewalls of the first lateral insulating layer and on the first faceted semiconductor blocks for the first and second regions of the SOI substrate, with the second and third lateral insulating layers having a faceted profile and filling the gaps between the inclined profile of each first faceted semiconductor block and the corresponding first lateral insulating layer;
removing, from the second region of the SOI substrate, the pair of first faceted semiconductor blocks and a portion of the second and third lateral insulating layers so that the remaining second and third lateral insulating layers have a faceted profile; and
forming on the second region of the SOI substrate a pair of second faceted semiconductor blocks of a second semiconductor material at a location where the pair of first faceted semiconductor blocks were removed, with the pair of second faceted semiconductor blocks matching a faceted profile of the corresponding first lateral insulating region and the second and third lateral insulating layers, the second semiconductor material having a second type of conductivity opposite the first type of conductivity for a second type of transistor;
with each pair of the first and second faceted semiconductor blocks having an upper surface coplanar with an upper surface of the third lateral insulating layer.

2. The method according to claim 1 , further comprising removing, from the first region of the SOI substrate, a portion of the second and second lateral insulating layers so that the remaining second and third lateral insulating layers have a faceted profile.

3. The method according to claim 1 , wherein the substrate comprises a fully-depleted silicon-on-insulator substrate.

4. The method according to claim 1 , wherein the first type of transistor for the first region of the SOI substrate comprises a PMOS transistor, and the second type of transistor for the second region of the SOI substrate comprises an NMOS transistor.

5. The method according to claim 1 , wherein the first type of transistor for the first region of the SOI substrate comprises an NMOS transistor, and the second type of transistor for the second region of the SOI substrate comprises a PMOS transistor.

6. The method according to claim 1 , wherein the first pair of faceted semiconductor blocks are epitaxially formed.

7. The method according to claim 1 , wherein the second pair of faceted semiconductor blocks are epitaxially formed.

8. A method for making a semiconductor device comprising:
forming a first gate region on a first region of a substrate, and a second gate region on a second region of the substrate;
forming a first lateral insulating layer on sidewalls of the first and second gate regions;
forming on the first and second regions of the substrate a respective pair of first faceted semiconductor blocks of a first semiconductor material adjacent the first lateral insulating layers, with a gap being formed between an inclined profile of each first faceted semiconductor block and a corresponding first lateral insulating layer, the first semiconductor material having a first type of conductivity for a first type of transistor;
forming second and third lateral insulating layers on sidewalls of the first lateral insulating layer and on the first faceted semiconductor blocks for the first and second regions of the substrate, with the second and third lateral insulating layers having a faceted profile and filling the gaps between the inclined profile of each first faceted semiconductor block and the corresponding first lateral insulating layer;
removing, from the second region of the substrate, the pair of first faceted semiconductor blocks and a portion of the second and third lateral insulating layers so that the remaining second and third lateral insulating layers have a faceted profile; and
forming on the second region of the substrate a pair of second faceted semiconductor blocks of a second semiconductor material at a location where the pair of first faceted semiconductor blocks were removed, with the pair of second faceted semiconductor blocks matching a faceted profile of the corresponding first lateral insulating region and the second and third lateral insulating layers, the second semiconductor material having a second type of conductivity opposite the first type of conductivity for a second type of transistor;
with each pair of the first and second faceted semiconductor blocks having an upper surface coplanar with an upper surface of the third lateral insulating layer.

9. The method according to claim 8 , further comprising removing, from the first region of the substrate, a portion of the second and third lateral insulating layers so that the remaining second and third lateral insulating layers have a faceted profile.

10. The method according to claim 8 , wherein the substrate comprises a fully-depleted silicon-on-insulator substrate.

11. The method according to claim 8 , wherein the first type of transistor for the first region of the substrate comprises a PMOS transistor, and the second type of transistor for the second region of the substrate comprises an NMOS transistor.

12. The method according to claim 8 , wherein the first type of transistor for the first region of the substrate comprises an NMOS transistor, and the second type of transistor for the second region of the substrate comprises a PMOS transistor.

13. The method according to claim 8 , wherein the first pair of faceted semiconductor blocks are epitaxially formed.

14. The method according to claim 8 , wherein the second pair of faceted semiconductor blocks are epitaxially formed.

15. An integrated circuit comprising:
a substrate comprising first and second regions;
at least one first type of transistor on the first region;
at least one second type of transistor on the second region; and
said at least one first and second type of transistors each comprising
a gate region,
a multilayer lateral insulating region on sidewalls of said gate region and on said substrate, said multilayer lateral insulating region comprising an inclined portion sloping away from said gate region, and
source and drain regions on said substrate, separated from said gate region by a corresponding multilayer lateral insulating region and having an inclined portion contacting the inclined portion of the said multilayer lateral insulating region, with each source and drain region having an upper surface coplanar with an upper surface of one of the layers from the corresponding multilayer lateral insulating region.

16. The integrated circuit according to claim 15 , wherein said at least one first type of transistor on the first region of said substrate c

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Barge David
• Garnier Philippe
• Campidelli Yves

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title