Memory device and method for putting a memory cell into a state with a reduced leakage current consumption

Patent metadata

Field	Value
Publication number	US-9412422-B2
Application number	US-201414338396-A
Country	US
Kind code	B2
Filing date	Jul 23, 2014
Priority date	Jul 23, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.

First claim

What is claimed is:

1. A memory device, comprising:
at least one memory cell and at least one virtual supply line coupled to the at least one memory cell;
wherein the memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.

2. The memory device of claim 1 ,
wherein the active access is a write access or a read access.

3. The memory device of claim 1 ,
wherein re-storing the charge comprises re-storing parasitic capacitances within the memory device.

4. The memory device of claim 1 ,
wherein the voltage potential present on the virtual supply line is altered by virtue of a parasitic capacitance of the virtual supply line being charged or discharged.

5. The memory device of claim 4 , further comprising:
at least one bit line coupled to the at least one memory cell;
wherein re-storing the charge comprises charging or discharging a parasitic bit line capacitance of the at least one bit line.

6. The memory device of claim 5 ,
wherein the active access is a write access or a read access; and
wherein the voltage potential present on the virtual supply line is decreased by a first voltage magnitude after the write access or the read access by virtue of the parasitic bit line capacitance being charged by a charge stored in the parasitic capacitance of the virtual supply line during the write access or the read access.

7. The memory device of claim 6 ,
wherein the voltage potential present on the virtual supply line comprises a positive supply potential.

8. The memory device of claim 5 ,
wherein the active access is a read access; and
wherein the voltage potential present on the virtual supply line is increased by a second voltage magnitude after the read access by virtue of the parasitic capacitance of the virtual supply line being charged by a charge stored in the parasitic bit line capacitance during the read access.

9. The memory device of claim 8 ,
wherein the voltage potential present on the virtual supply line comprises a ground potential.

10. The memory device of claim 5 ,
wherein the at least one virtual supply line comprises a first virtual supply line and a second virtual supply line.

11. The memory device of claim 10 ,
wherein the active access is a write access, and wherein the voltage potential present on the first virtual supply line is decreased by a first voltage magnitude after the write access by virtue of the parasitic bit line capacitance being charged by a charge stored in a parasitic capacitance of the first virtual supply line during the write access.

12. The memory device of claim 10 ,
wherein the active access is a read access; and
wherein the voltage potential present on the second virtual supply line is increased by a second voltage magnitude after the read access by virtue of a parasitic capacitance of the second virtual supply line being charged by a charge stored in the parasitic bit line capacitance during the read access.

13. The memory device of claim 1 , further comprising:
at least one supply line; and
at least one bias circuit coupled to the virtual supply line and to the supply line in order, during the active access, to match a voltage potential present on the virtual supply line to a voltage potential present on the supply line.

Assignees

• Infineon Technologies Ag

Inventors

• Huber Peter

Classifications

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/407

  for memory cells of the field-effect type · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title