Method and system for platform management messages across peripheral component interconnect express (PCIe) segments

Patent metadata

Field	Value
Publication number	US-9411762-B2
Application number	US-201313843066-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.

First claim

What is claimed is:

1. A method to manage platform management messages comprising:
receiving a serial differential, point-to-point interconnect management message as a media-independent protocol packet, wherein the media-independent protocol packet utilizes a Management Component Transport Protocol (MCTP) over Peripheral Component Interconnect (PCI) Express (PCIe) packet format allowing an extension of the serial, differential, point-to-point interconnect;
extracting a bus segment identifier and an endpoint identifier from distinct portions of a destination endpoint identifier field of the packet having the MCTP over PCIe packet format; and
routing the received management message using the bus segment identifier and the endpoint identifier, including routing the received management message to a bus segment uniquely identified by the bus segment identifier, including using a local segment identifier register to select between use of the endpoint identifier or target bus identifier field bits in order to lookup a target identifier with a MCTP source address decoder.

2. The method of claim 1 , further comprising determining whether to interpret the portion of a destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message as a bus segment identifier by checking a setting within a basic input/out system (BIOS) of the computing system.

3. The method of claim 2 , wherein the BIOS of the computing system specifies a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier.

4. The method of claim 2 , wherein the setting within the BIOS indicates whether to interpret the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message as a serial differential, point-to-point interconnect bus segment identifier or to interpret a portion of a target identifier field of the format allowing an extension of the serial, differential, point-to-point interconnect as a processor node identifier.

5. The method of claim 4 , wherein the setting within the BIOS of the computing system indicates that the portion of a target identifier field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message being interpreted as a processor node identifier, wherein the serial differential, point-to-point interconnect management message is routed to the identified processor node, and wherein the identified processor node is coupled with a first processor from which the serial differential, point-to-point interconnect message is received through a point-to-point processor interconnect.

6. The method of claim 2 , furthering comprising determining a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier prior to extracting the serial differential, point-to-point interconnect bus segment identifier when the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is determined to be interpreted as the serial differential, point-to-point interconnect bus segment identifier.

7. The method of claim 1 , wherein the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier is one of one bit, two bits, three bits, four bits, and five bits.

8. The method of claim 1 , wherein routing the serial differential, point-to-point interconnect management message comprises comparing the serial differential, point-to-point interconnect bus segment identifier within the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect with a register of the root complex containing a segment identifier associated with a first processor.

9. The method of claim 8 , wherein the serial differential, point-to-point interconnect management message contains the serial differential, point-to-point interconnect bus segment identifier being inserted by a second processor of the computing system.

10. The method of claim 9 , wherein the second processor of the computing system further contain a serial differential, point-to-point interconnect bus segment identifier inserted in a source field.

11. An apparatus, comprising:
a root complex, the root complex including:
message logic configured to receive a serial differential, point-to-point interconnect management message, the serial differential, point-to-point interconnect management message to be transmitted as a media-independent protocol packet, wherein the media-independent protocol packet is to utilize a Management Component Transport Protocol (MCTP) over Peripheral Component Interconnect (PCI) Express (PCIe) packet format allowing an extension of the serial, differential, point-to-point interconnect;
decoder logic configured to determine whether to interpret a portion of an endpoint destination field of the packet having the MCTP over PCIe packet format allowing an extension of the serial, differential, point-to-point interconnect of the serial differential, point-to-point interconnect management message that is to be received as a serial differential, point-to-point interconnect bus segment identifier;
extraction logic configured to extract the serial differential, point-to-point interconnect bus segment identifier and an endpoint identifier from distinct portions of the destination field of the packet having the MCTP over PCIe packet format when a portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is determined to be interpreted as a serial differential, point-to-point interconnect bus segment identifier; and
management logic configured to route the received serial differential, point-to-point interconnect management message, using the point-to-point interconnect bus segment identifier and the endpoint identifier, to a serial differential, point-to-point interconnect bus segment to be uniquely specified by the serial differential, point-to-point interconnect bus segment identifier within the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect, the management logic including a local segment identifier register to select between use of the endpoint identifier or target bus identifier field bits in order to lookup a target identifier with a MCTP source address decoder.

12. The apparatus of claim 11 , wherein the computing system further includes a basic input/out system (BIOS) configured to store a setting for the computing system to determine whether to interpret the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message being a serial diff

Assignees

• Natu Mahesh
• Nair Mohan
• Intel Corp

Inventors

• Natu Mahesh
• Nair Mohan

Classifications

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title