Clock data recovery circuit and clock data recovery method

Patent metadata

Field	Value
Publication number	US-9411594-B2
Application number	US-201213589354-A
Country	US
Kind code	B2
Filing date	Aug 20, 2012
Priority date	Aug 22, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A processor includes: an arithmetic unit configured to execute instructions; an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes; and an interrupt register configured to receive interrupt signals, wherein the instruction decode part includes an instruction code map that stores the opcodes in correspondence to instructions and outputs the opcodes in accordance with the instructions inputted, and the instruction code map stores a plurality of sets of opcodes to be output as switch opcodes corresponding to additional instructions, the additional instructions are a part of the instructions, and switches the sets of the switch opcodes in accordance with the interrupt signal.

First claim

What is claimed is:

1. A processor comprising:
an arithmetic unit configured to execute instructions;
an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes;
an interrupt register configured to receive an interrupt signal; and
a sequencer configured to store a series of instructions to be processed by continuous instructions included in the instructions, wherein the sequencer outputs the series of instructions to the instruction decode part in response to the instruction decode part detecting the continuous instructions,
wherein the instruction decode part comprises an instruction code map that is configured to store the opcodes in correspondence to instructions and to output the opcodes in accordance with the instructions inputted, and
the instruction code map is further configured to store a plurality of opcodes to be output to a second arithmetic unit as switch opcodes corresponding to additional instructions, the additional instructions being a part of the instructions, and to switch the plurality of the switch opcodes in accordance with the interrupt signal.

2. The processor according to claim 1 , wherein the instruction decode part further comprises:
a general instruction decoder configured to decode general instructions except the additional instructions and to output general opcodes,
a plurality of additional instruction decoders corresponding to the additional instructions, the plurality of additional instruction decoders being configured to decode the additional instructions and to output additional opcodes,
an opcode selection circuit configured to select the additional opcodes output from the plurality of additional instruction decoders in accordance with data of the interrupt register, and
a final selection circuit configured to select one of the general opcode output from the general instruction decoder and the additional opcodes output from the opcode selection circuit.

3. The processor according to claim 1 , wherein
the interrupt signal has a multi-interrupt relationship, and
the interrupt register has a stacked structure.

4. The processor according to claim 2 , wherein
the interrupt signal has a multi-interrupt relationship, and
the interrupt register has a stacked structure.

5. A processor comprising:
an arithmetic unit configured to execute instructions;
an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes;
an interrupt register configured to receive an interrupt signal; and
a sequencer configured to store a series of instructions to be processed by continuous instructions included in the instructions, wherein the sequencer outputs the series of instructions to the instruction decode part in response to the instruction decode part detecting the continuous instructions, and
wherein the instruction decode part comprises an instruction code map that is configured to store the opcodes in correspondence to instructions and to output the opcodes in accordance with the instructions inputted, and wherein the instruction code map is further configured to store a plurality of opcodes to be output as switch opcodes corresponding to additional instructions, the additional instructions being a part of the instructions, and to switch the plurality of the switch opcodes in accordance with the interrupt signal.

6. The processor according to claim 5 , wherein
the interrupt signal has a multi-interrupt relationship, and
the interrupt register has a stacked structure.

7. The processor according to claim 5 , wherein the instruction decode part comprises:
a general instruction decoder configured to decode general instructions except the additional instructions and to output general opcodes;
a plurality of additional instruction decoders corresponding to the additional instructions, the plurality of additional instruction decoders being configured to decode the additional instructions and to output additional opcodes;
an opcode selection circuit configured to select the additional opcodes output from the plurality of additional instruction decoders in accordance with data of the interrupt register; and
a final selection circuit configured to select one of the general opcode output from the general instruction decoder and the additional opcodes output from the opcode selection circuit.

8. The processor according to claim 7 , wherein
the interrupt signal has a multi-interrupt relationship, and
the interrupt register has a stacked structure.

Assignees

• Tsuji Masayuki
• Cypress Semiconductor Corp

Inventors

• Tsuji Masayuki

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/30196 Primary

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title