Memory systems and methods for controlling the timing of receiving read data

Patent metadata

Field	Value
Publication number	US-9411538-B2
Application number	US-201414280861-A
Country	US
Kind code	B2
Filing date	May 19, 2014
Priority date	May 29, 2008
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to each of the plurality of memory devices and configured to receive first and second commands consecutively, the controller further configured to provide the first command to a first memory device of the plurality of memory devices and further configured to provide the second command with a first delay responsive to the second command being associated with the first memory device and to provide the second command with a second delay responsive to the second command being associated with a second memory device of the plurality of memory devices.

2. The apparatus of claim 1 , wherein the second delay is greater than the first delay.

3. The apparatus of claim 2 , wherein the second delay is one-half of a clock period greater than the first delay.

4. The apparatus of claim 1 , wherein the controller is further configured to receive a third command, the controller configured to provide the third command with the first delay responsive to the second and third commands being associated with a same memory device of the plurality of memory devices and to provide the third command with the second delay responsive to the second and third commands being associated with different memory devices of the plurality of memory devices.

5. The apparatus of claim 1 , wherein each of the plurality of memory devices includes a capture circuit for selectively capturing commands based on a control signal.

6. The apparatus of claim 5 , wherein the controller is configured to assert the control signal responsive to providing of the first command.

7. The apparatus of claim 6 , wherein the controller is configured to assert the control signal at a first time after providing the first command and to assert the control signal at a second time after providing the first command, the first time based on the first delay and the second time based on the second delay.

8. A method, comprising:
receiving a first command;
providing the first command to a first memory device;
receiving a second command;
if the second command is associated with the first memory device, providing the second command to the first memory device after a first delay; and
if the second command is associated with a second memory device different than the first memory device, providing the second command to the second memory device after a second delay greater than the first delay.

9. The method of claim 8 , further comprising:
responsive to providing the first command, asserting a control signal at a first time and at a second time, the first time based on the first delay and the second time based on the second delay.

10. The method of claim 9 , wherein asserting a control signal at a first time and at a second time, the first time based on the first delay and the second time based on the second delay comprises:
delaying the first command.

11. The method of claim 8 , further comprising:
asserting a control signal after an access time; and
receiving read data associated with the first command.

12. The method of claim 8 , further comprising:
receiving a third command; and
if the third command is associated with the second memory device, providing the third command to the second memory device after the first delay; and
if the third command is associated with a third memory device different than the second memory device, providing the third command to the third memory device after the second delay.

13. The method of claim 8 , wherein the second delay is one-half of a clock period greater than the first delay.

14. A method, comprising:
receiving a first command;
providing a first command to a first memory device;
providing a first output control signal to the first memory device;
receiving a second command;
if the second command is associated with the first memory device:
providing the second command to the first memory device; and
providing a second output control signal to the first memory device after a first delay; and

if the second command is associated with a second memory device different than the first memory device:
providing the second command to the second memory device; and
providing the second output control signal to the second memory device after a second delay greater than the first delay.

15. The method of claim 14 , further comprising:
before receiving the second command, receiving read data associated with the first command.

16. The method of claim 14 , wherein providing the second output control signal to the second memory device after a second delay greater than the first delay comprises:
providing the second output control signal after at least one unit time interval and less than one controller clock cycle.

17. The method of claim 14 , wherein providing a second output control signal to the first memory device after a first delay comprises:
providing the second output control signal after an access time.

18. The method of claim 14 , further comprising:
delaying a read command by one controller clock cycle.

19. The method of claim 14 , wherein the second delay is based on the first delay.

20. The method of claim 19 , wherein the second delay includes the first delay and additionally a one-quarter of a clock period delay.

Assignees

• Micron Technology Inc

Inventors

• Laberge Paul A
• Johnson James B

Classifications

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title