Memory system and method using stacked memory device dice, and system using the memory system

Patent metadata

Field	Value
Publication number	US-9275698-B2
Application number	US-201414339680-A
Country	US
Kind code	B2
Filing date	Jul 24, 2014
Priority date	Jul 21, 2008
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory system including a plurality of memory devices and a control circuit coupled to the plurality of memory devices, the control circuit configured to adjust a plurality of read strobe signals provided to respective ones of the plurality of memory devices to cause read data to be provided by each of the plurality of memory devices at substantially the same time.

2. The apparatus of claim 1 , wherein the control circuit comprises:
a timing control circuit configured to provide a plurality of read strobe signals and a plurality of timing control signals to a plurality of strobe timing adjustment circuits, the plurality of strobe timing adjustment circuits configured to adjust the timing of the plurality of read strobe signals and provide a plurality of adjusted read strobe signals to respective ones of the plurality of memory devices.

3. The apparatus of claim 2 , wherein a strobe timing adjustment circuit of the plurality of strobe timing adjustment circuits is configured to receive a read strobe signal of the plurality of read strobe signals and a timing control signal of the plurality of timing control signals, the strobe timing adjustment circuit of the plurality of strobe timing adjustment circuits further configured to provide an adjusted clock signal based, at least in part, on the timing control signal of the plurality of timing control signals and to provide the read strobe signal of the plurality of read strobe signals responsive to the adjusted clock signal.

4. The apparatus of claim 1 , wherein the control circuit comprises a plurality of strobe timing adjustment circuits, a strobe timing adjustment circuit of the plurality of strobe timing adjustment circuits comprising:
a register configured to store the respective read strobe signal and apply a plurality of bits of the stored read strobe signal to respective output terminals;
a serializing circuit configured to receive the bits of the stored read strobe signal from the register, the serializing circuit further configured to output the bits of the stored read strobe signal in serial form at a time determined by an adjusted clock signal; and
a delay circuit configured to receive a clock signal and output the adjusted clock signal with a delay corresponding to a timing control signal.

5. The apparatus of claim 1 , wherein a read strobe signal of the plurality of read strobe signals comprises a pattern of alternating high and low logic levels.

6. The apparatus of claim 1 , wherein the plurality of read strobe signals is adjusted based, at least in part on, a distance between the control circuit and a memory device of the plurality of memory devices.

7. The apparatus of claim 1 , wherein groupings of the plurality of memory devices are included on each memory device dice of a plurality of memory device dice.

8. An apparatus, comprising:
a logic circuit configured to control timing of a plurality of data strobe signals provided to a plurality of memory devices, wherein the logic circuit comprises:
a plurality of timing adjustment circuits coupled to a respective one of the plurality of memory devices and configured to provide a respective adjusted data strobe signal to each of the plurality of memory devices based at least in part on a timing control signal; and
a timing control circuit configured to provide a respective one of the plurality of data strobe signals and a respective one of a plurality of timing control signals to each of the plurality of strobe timing adjustment circuits.

9. The apparatus of claim 8 , the logic circuit further comprising:
a plurality of receivers configured to receive the data from a respective one of the plurality of memory devices, and wherein each of the plurality of receivers is further configured to capture the data based on the same clock signal.

10. The apparatus of claim 8 , the logic circuit further comprising:
a plurality of transmitters configured to transmit data to a respective one of the plurality of memories, and wherein each of the plurality of transmitters is further configured to serialize the data to be provided to a respective one of the plurality of memory devices.

11. The apparatus of claim 8 , wherein a value of each of the plurality of timing control signals is determined from a training sequence performed by the logic circuit.

12. The apparatus of claim 8 , wherein each of the data strobe signals of the plurality of data strobe signals is adjusted based, at least in part on, a distance between the respective memory device of the plurality of memory devices and the logic circuit.

13. The apparatus of claim 8 , wherein the logic circuit provides the plurality of data strobe signals based, at least in part, on a received data/command packet.

14. The apparatus of claim 8 , wherein the logic circuit is configured to provide read data without any additional timing adjustments regardless of which one of the plurality of memory devices is the originator of the read data.

15. The apparatus of claim 8 , wherein the logic circuit is configured to control the timing of the data strobe signals to cause write data to arrive at the plurality of memory devices at substantially the same time.

16. The apparatus of claim 8 , wherein each of the plurality of data strobe signals is provided to a respective one of the plurality of memory devices by silicon through vias.

17. The apparatus of claim 8 , wherein the plurality of data strobe signals is in a pattern of alternating high and low logic levels.

18. A method, comprising:
receiving a command at a logic circuit coupled to a plurality of memory devices;
generating a plurality of data strobe signals, wherein each of the plurality of data strobe signals is provided to a respective one of the plurality of data strobe signals;
selectively delaying a data strobe signal of the plurality of data strobe signals based at least in part on a respective timing control signal of a plurality of timing control signals; and
receiving the plurality of data strobe signals at the plurality of memory devices, wherein the plurality of memory devices perform at substantially the same time responsive to the respective data strobe signal.

19. The method of claim 18 , wherein the command is a read command and the plurality of memory devices provide read data to the logic circuit at substantially the same time.

20. The method of claim 18 , wherein the command is a write command and the plurality of memory devices receive write data at substantially the same time.

21. The method of claim 18 , wherein each of the plurality of timing control signals is based at least in part on a physical distance the respective one of the plurality of memory devices is from the logic circuit.

Assignees

• Micron Technology Inc

Inventors

• Laberge Paul A
• Jeddeloh Joseph M
• Johnson James B

Classifications

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title