Systems and methods for distributing an aging burden among processor cores

Patent metadata

Field	Value
Publication number	US-9407272-B2
Application number	US-201113341748-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Aug 17, 2011
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

First claim

What is claimed is:

1. A system for distributing aging burden among a plurality of processor cores comprising:
a processor including the plurality of processor cores comprised of semiconductor material; and
a Power Management Unit (PMU) coupled to the processor, wherein the PMU is configured to:
track, using a plurality of different types of aging mechanisms, aging of the respective semiconductor material of the processor cores, wherein the aging mechanisms include detection of slowed frequency performance, threshold voltage variation, and substrate current level of the respective processor cores,
monitor, based on the tracked plurality of different types of aging mechanisms, a difference in aging of the respective semiconductor material during respective lifetimes of the plurality of processor cores,
determine whether the difference in aging between the respective semiconductor material of a first processor core of the plurality of processor cores and a second processor core of the plurality of processor cores has exceeded a predetermined threshold, and
reassign, in response to determining that the difference in aging has exceeded the predetermined threshold, an instruction assigned to the first processor core of the plurality of processor cores to the second processor core of the plurality of processor cores for execution if the respective semiconductor material of the first processor core of the plurality of processor cores has aged more than the respective semiconductor material of the second processor core of the plurality of processor cores.

2. The system of claim 1 , wherein the PMU is further configured to:
reassign, in response to determining that the difference in aging has exceeded the predetermined threshold, an instruction assigned to the second processor core of the plurality of processor cores to the first processor core of the plurality of processor cores for execution if the respective semiconductor material of the second processor core of the plurality of processor cores has aged more than the respective semiconductor material of the first processor core of the plurality of processor cores.

3. The system of claim 1 , wherein the PMU is further configured to:
monitor loads on the plurality of processor cores;
predict, based on the monitored loads, an increased load on the first processor core of the plurality of processor cores; and
pre-charge the first processor core of the plurality of processor cores responsive to predicting the increased load.

4. The system of claim 1 , wherein the PMU is further configured to:
monitor loads on the plurality of processor cores;
predict, based on the monitored loads, an increased load on the first processor core of the plurality of processor cores; and
reduce a processing frequency of the first processor core of the plurality of processor cores responsive to predicting the increased load.

5. The system of claim 1 , wherein the PMU is further configured to:
monitor temperature of the plurality of processor cores;
determine whether a temperature of the first processor core of the plurality of processor cores has exceeded a temperature threshold; and
select a cooler processor core of the plurality of processor cores for execution of an instruction assigned to the first processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold.

6. The system of claim 1 , wherein the PMU is further configured to:
monitor temperature of the plurality of processor cores, wherein the first processor core of the plurality of processor cores is configured to process a first thread of a multi-threaded application, and wherein a second processor core of the plurality of processor cores is configured to process a second thread of the multi-threaded application;
determine whether a temperature of the first processor core of the plurality of processor cores has exceeded a temperature threshold;
determine whether a cooler processor core of the plurality of processor cores is available to process the first thread; and
process the first thread using the cooler processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold and that the cooler processor core of the plurality of processor cores is available to process the first thread.

7. The system of claim 6 , wherein the PMU is further configured to:
process the first thread and the second thread using the second processor core of the plurality of processor cores responsive to determining that the temperature of the first processor core of the plurality of processor cores has exceeded the temperature threshold and that no cooler processor core of the plurality of processor cores other than the second processor core of the plurality of processor cores is available to process the first thread.

8. The system of claim 1 , wherein the PMU is further configured to:
determine a relative difference in aging among the plurality of processor cores; and
assign, based on the determined relative difference in aging, power states to the plurality of processor cores.

9. The system of claim 1 , wherein the PMU is further configured to:
determine a relative difference in temperature among the plurality of processor cores; and
assign, based on the determined relative difference in temperature, power states to the plurality of processor cores.

10. A system for distributing aging burden among a plurality of processor cores comprising:
a processor including the plurality of processor cores; and
a Power Management Unit (PMU) coupled to the processor, wherein the PMU is configured to:
track aging of the plurality of processor cores based on changes in device characteristics of the respective plurality of processor cores, wherein the changes in device characteristics comprise slowed frequency performance, threshold voltage variation, and substrate current level in the respective processor cores,
monitor a difference in aging among the plurality of processor cores,
rotate execution of an application among the plurality of processor cores based on a predetermined aging scheme such that:
the plurality of processor cores age approximately evenly over respective lifetimes of the plurality of processor cores,
the difference in aging among the plurality of processor cores does not exceed a predetermined aging threshold, and
the execution of the application is transferred from a first processor core of the plurality of processor cores to a second processor core of the plurality of processor cores in response to determining that a first aging threshold corresponding to the first processor core of the plurality of processor cores has been reached and the second processor core of the plurality of processor cores has aged less than the first processor core of the plurality of processor cores.

11. The system of claim 10 , wherein the PMU is further configured to execute the application on the first processor core of the plurality of processor cores and the second processor core of the plurality of processor cores in parallel to determine whether the first aging threshold of the first processor core of the plurality of processor cores has been reached.

12. The system of claim 10 , wherein the PMU is further configured to:
determine a relative difference in temperature of the plurality of processor cores;
assign a first power state to the first processor core of the plurality of processor cores responsive to determining th

Assignees

• Penzes Paul
• Fullerton Mark
• Jung Hwisung
• Walley John
• Sippel Tim
• Kothari Love
• Broadcom Corp

Inventors

• Penzes Paul
• Fullerton Mark
• Jung Hwisung
• Walley John
• Sippel Tim
• Kothari Love

Classifications

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• G06F12/14

  Protection against unauthorised use of memory {or access to memory} · CPC title

• H03L7/097

  using a comparator for comparing the voltages obtained from two frequency to voltage converters · CPC title