Interposer package-on-package structure

Patent metadata

Field	Value
Publication number	US-9406636-B2
Application number	US-201514715484-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	Sep 11, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
an integrated circuit (IC) die;
an interposer substrate;
a bottom substrate;
a mold compound disposed on a first surface of the bottom substrate, the IC die being at least partially encapsulated by the mold compound, the mold compound being coupled to the interposer substrate via adhesive material;
a first plurality of electrical contact members coupled to the IC die, the IC die being coupled to the first surface of the bottom substrate via the first plurality of electrical contact members;
a second plurality of electrical contact members coupled to a second surface of the bottom substrate; and
a third plurality of electrical contact members coupled to the interposer substrate and the first surface of the bottom substrate, at least a portion of the third plurality of electrical contact members extending above the mold compound.

2. The integrated circuit package of claim 1 , wherein the IC die is in contact with the adhesive material.

3. The integrated circuit package of claim 1 , wherein the adhesive material is disposed within an air gap formed between the IC die and the interposer substrate.

4. The integrated circuit package of claim 1 , wherein the IC die is encapsulated by the mold compound, and wherein the IC die is coupled to the interposer substrate via the mold compound and the adhesive material.

5. The integrated circuit package of claim 1 , wherein the adhesive material is disposed within an air gap formed between the mold compound and the interposer substrate.

6. The integrated circuit package of claim 1 , wherein the adhesive material is disposed on a surface periphery of the mold compound.

7. The integrated circuit package of claim 1 , wherein the mold compound has one or more trenches, and wherein at least a portion of the third plurality of electrical contact members is disposed within the one or more trenches.

8. The integrated circuit package of claim 1 , further comprising underfill material disposed between the IC die and the first surface of the bottom substrate, the underfill material being in contact with the mold compound.

9. The integrated circuit package of claim 8 , wherein the underfill material and the adhesive material are formed of a same material.

10. The integrated circuit package of claim 1 , wherein at least a portion of the adhesive material is disposed on a plurality of locations of a surface of the IC die.

11. An integrated circuit package, comprising:
an integrated circuit (IC) die;
an interposer substrate;
a bottom substrate;
a mold compound disposed on a first surface of the bottom substrate, the mold compound being in contact with the IC die, the interposer substrate being coupled to the mold compound and the IC die via adhesive material;
a set of conductive posts coupled to the IC die, the IC die being coupled to the first surface of the bottom substrate via the set of conductive posts, the set of conductive posts being encapsulated by underfill material disposed on the bottom substrate;
a first set of conductive bumps coupled to a second surface of the bottom substrate; and
a second set of conductive bumps coupled to the interposer substrate and the first surface of the bottom substrate, wherein at least a portion of the second set of conductive bumps extend above the mold compound.

12. The integrated circuit package of claim 11 , wherein the IC die is partially encapsulated by the mold compound, and wherein the IC die is in contact with the adhesive material.

13. The integrated circuit package of claim 12 , wherein the adhesive material is disposed within an air gap formed between the IC die and the interposer substrate.

14. The integrated circuit package of claim 11 , wherein the IC die is encapsulated by the mold compound, and wherein the IC die is coupled to the interposer substrate via the mold compound and the adhesive material.

15. The integrated circuit package of claim 14 , wherein the adhesive material is disposed within an air gap formed between the mold compound and the interposer substrate.

16. The integrated circuit package of claim 11 , wherein the adhesive material is disposed on a surface periphery of the mold compound.

17. The integrated circuit package of claim 11 , wherein the surface of the mold compound has one or more trenches, and wherein at least a portion of the second set of conductive bumps is disposed within the one or more trenches.

18. The integrated circuit package of claim 11 , wherein the underfill material is disposed between the IC die and the first surface of the bottom substrate, the underfill material being in contact with the mold compound.

19. The integrated circuit package of claim 11 , wherein the underfill material and the adhesive material are formed of a same material.

20. The integrated circuit package of claim 11 , wherein the adhesive material is disposed on a plurality of locations of a surface of the mold compound.

Assignees

• Broadcom Corp

Inventors

• Zhao Sam Ziqun
• Khan Rezaur Rahman

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title