Systems and methods for eliminating seams in atomic layer deposition of silicon dioxide film in gap fill applications

Patent metadata

Field	Value
Publication number	US-9406544-B1
Application number	US-201514737760-A
Country	US
Kind code	B1
Filing date	Jun 12, 2015
Priority date	Jun 12, 2015
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method for filling a trench in a substrate includes partially filling the trench with a first silicon dioxide layer. An amorphous silicon layer is deposited on the silicon dioxide layer. The trench is filled with a second silicon dioxide layer. An oxidation treatment is performed on the substrate to oxidize the amorphous silicon layer.

First claim

What is claimed is:

1. A method for filling a trench in a substrate, comprising:
partially filling the trench with a first silicon dioxide layer;
depositing an amorphous silicon layer on the silicon dioxide layer;
filling the trench by depositing a second silicon dioxide layer directly on the amorphous silicon layer using an atomic layer deposition process; and
performing an oxidation treatment on the substrate to oxidize the amorphous silicon layer.

2. The method of claim 1 , wherein the trench comprises a shallow trench insulator (STI).

3. The method of claim 1 , wherein the first silicon dioxide layer is deposited using the ALD process.

4. The method of claim 3 , wherein the ALD process deposits conformal film.

5. The method of claim 3 , wherein the ALD process uses process gases including Bis(tertiary-butyl-amino)silane (BTBAS), nitrous oxide (N 2 O) and oxygen (O 2 ).

6. The method of claim 1 , where the oxidation treatment includes:
heating the substrate to a process temperature; and
exposing the substrate to water vapor.

7. The method of claim 1 , where the oxidation treatment includes:
heating the substrate to a process temperature; and
exposing the substrate to molecular oxygen.

8. The method of claim 6 , wherein the substrate is heated in a furnace.

9. The method of claim 6 , wherein the process temperature is between 600° C. and 1000° C.

10. The method of claim 6 , wherein the process temperature is between 875° C. and 925° C.

11. The method of claim 6 , wherein the process time is between 1 hour and 5 hours.

12. The method of claim 1 , wherein the trench has an aspect ratio that is greater than 4:1.

13. The method of claim 1 , wherein the trench has an aspect ratio that is greater than 8:1.

14. The method of claim 1 , wherein the amorphous silicon layer is deposited using thermal chemical vapor deposition (CVD) process.

15. The method of claim 14 , wherein the thermal CVD process uses disilane as a process gas.

16. The method of claim 1 , wherein the amorphous silicon layer has a thickness of 2 nm to 4 nm.

Assignees

• Lam Res Corp

Inventors

• Tang Wei
• Park Jason Daejin
• Van Schravendijk Bart
• Ashtiani Kaihan

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W10/0142

  the dielectric materials being chemical transformed from non-dielectric materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title