Semiconductor wafer structure

Patent metadata

Field	Value
Publication number	US-9406499-B2
Application number	US-201414178814-A
Country	US
Kind code	B2
Filing date	Feb 12, 2014
Priority date	Feb 12, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first wafer including a plurality of protrusions protruded from and elongated across the first wafer;
a second wafer including a second surface attached with the plurality of protrusions,
wherein a plurality of passages are intervally configured between the plurality of protrusions and elongated across the first wafer and the second surface of the second wafer.

2. The semiconductor structure of claim 1 , wherein the plurality of passages are substantially parallel to each other.

3. The semiconductor structure of claim 1 , wherein the first wafer is a carrier wafer or a handle wafer including silicon.

4. The semiconductor structure of claim 1 , wherein an area ratio of the plurality of protrusions to the plurality of passages is about 1:10 to about 1:2.

5. The semiconductor structure of claim 1 , wherein the plurality of passages are configured to evacuate air or moisture along each of the plurality of passages disposed.

6. The semiconductor structure of claim 1 , wherein the plurality of protrusions are spaced from each other in a consistent interval.

7. The semiconductor structure of claim 1 , wherein the first wafer or the second wafer is in a circular shape, and each of the plurality of protrusions has a top surface in a rectangular or quadrilateral shape.

8. The semiconductor structure of claim 1 , wherein the plurality of protrusions are integrally formed with the first wafer.

9. The semiconductor structure of claim 1 , wherein each of the plurality of protrusions has a height of about 100 um to about 500 um.

10. The semiconductor structure of claim 1 , wherein the first wafer has a thickness of about 400 um to about 800 um.

11. The semiconductor structure of claim 1 , wherein the plurality of protrusions include silicon.

12. A semiconductor structure, comprising:
a first wafer including a first surface and a first periphery;
a second wafer including a second planar surface and a second periphery;
a plurality of protrusions protruded from the first surface of the first wafer and attached to the second planar surface of the second wafer to bond the first wafer with the second wafer; and
a plurality of recesses disposed between the first wafer and the second wafer and spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the second periphery of the second wafer, elongated across the second surface of the second wafer, and configured to evacuate air or moisture between the first surface and the second planar surface out from the first periphery or the second periphery.

13. The semiconductor structure of claim 12 , wherein each of the plurality of protrusions has a top surface disposed on the second planar surface of the second wafer.

14. The semiconductor structure of claim 12 , wherein the first wafer and the second wafer are in substantially same dimension and shape.

15. The semiconductor structure of claim 12 , wherein the second wafer is a device wafer with a thickness of about 1 um to about 5 um.

16. The semiconductor structure of claim 12 , wherein a ratio of a total interfacing area between the plurality of protrusions and the second planar surface to an area of the second planar surface is about 1:10 to about 1:2.

17. A semiconductor structure, comprising:
a carrier wafer including a plurality of protrusions protruded from and elongated across the carrier wafer; and
a device wafer including a surface attached with the plurality of protrusions; and
a passage disposed between two of the plurality of protrusions, and configured to allow air or moisture flowing along the passage.

18. The semiconductor structure of claim 17 , wherein the plurality of protrusions are extended parallel to each other.

19. The semiconductor structure of claim 17 , wherein the air or the moisture is laterally evacuatable along the passage.

20. The semiconductor structure of claim 17 , wherein each of the plurality of protrusions includes an end disposed adjacent to a periphery of the carrier wafer or the device wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chen-Chun
• Chen Chiu-Jung
• Tsai Fu-Tsun
• Jangjian Shiu-Ko
• Jeng Chi-Cherng
• Chen Hsin-Chi

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P90/126

  by chemical etching · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/642

  Chemical etching · CPC title