Systems, devices, and methods for analog processing

Patent metadata

Field	Value
Publication number	US-9406026-B2
Application number	US-201514868019-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Mar 24, 2008
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

First claim

The invention claimed is:

1. A quantum processor, comprising:
a plurality of qubits and one or more coupling devices arranged to form a topology for embedding a bipartite graph, or portion thereof, the topology comprising a plurality of subtopologies of qubits and coupling devices, the plurality of subtopologies arranged in a grid, each subtopology of qubits respectively comprising:
a respective first set of qubits;
a respective second set of qubits, each of of the qubits in the respective second set of qubits which crosses at least one of the qubits of the first set of qubits; and
a respective first set of coupling devices, each coupling device in the respective first set of coupling devices selectively operable to directly communicatively couple one of the qubits in the respective first set of qubits to one of the qubits in the respective second set of qubits,

the topology comprising a second set of coupling devices, each coupling device in the second set of coupling devices selectively operable to communicatively couple one of the qubits in one of the plurality of subtopologies with one of the qubits in another of the plurality of subtopologies.

2. The quantum processor of claim 1 wherein a plurality of nodes of the bipartite graph are embedded into a respective qubit, and one or more edges of the bipartite graph are embedded into a respective coupling device.

3. The quantum processor of claim 1 wherein the quantum processor is a superconducting quantum processor, and the respective first and the respective second set of qubits are superconducting qubits.

4. The quantum processor of claim 3 wherein each qubit of the respective first and the respective second set of qubits comprises an elongate loop of superconducting material interrupted by at least one Josephson junction.

5. The quantum processor of claim 4 wherein each qubit of the respective first set of qubits is laid out horizontally, and each qubit of the respective second set of qubits is laid out vertically.

6. The quantum processor of claim 1 wherein each coupling device of the respective first and the second set of coupling devices is selectively operable to couple a respective pair of qubits selected from the respective first and the respective second set of qubits in the plurality of subtopologies by at least one of a ferromagnetic coupling, an anti-ferromagnetic coupling, a zero coupling, or a transverse coupling.

7. The quantum processor of claim 1 wherein the bipartite graph is a complete graph.

8. The quantum processor of claim 7 wherein, for at least one of the plurality of subtopologies, the respective first set of qubits is a first set of four qubits, the respective second set of qubits is a second set of four qubits, and the respective first set of coupling devices is selectively operable to embed a complete K 4 graph.

9. The quantum processor of claim 7 wherein the plurality of subtopologies includes three subtopologies, and wherein, for each of the three subtopologies respectively, the respective first set of qubits is a first set of four qubits, the respective second set of qubits is a second set of four qubits, and the respective first set of coupling devices is selectively operable to embed a complete K 4 graph, the second set of coupling devices selectively operable to embed a complete K 8 graph in the three subtopologies.

10. A method of embedding a bipartite graph, or portion thereof, in a quantum processor, the quantum processor including a plurality of qubits and one or more coupling devices arranged to form a topology, the topology including a plurality of subtopologies of qubits and coupling devices, the plurality of subtopologies arranged in a grid, each subtopology of qubits respectively including a respective first set of qubits; a respective second set of qubits, each of the qubits in the respective second set of qubits which crosses at least one of the qubits of the first set of qubits; a respective first set of coupling devices, each coupling device in the respective first set of coupling devices selectively operable to directly communicatively couple one of the qubits in the respective first set of qubits to one of the qubits in the respective second set of qubits, and the topology further including a second set of coupling devices, each coupling device in the second set of coupling devices selectively operable to communicatively couple one of the qubits in one of the plurality of subtopologies with one of the qubits in another of the plurality of subtopologies, the method comprising:
embedding a plurality of nodes of the bipartite graph into a respective qubit; and
embedding one or more edges of the bipartite graph into a respective coupling device.

11. The method of claim 10 wherein embedding a plurality of nodes of the bipartite graph into a respective qubit includes embedding a plurality of nodes of the bipartite graph into a respective superconducting qubit.

12. The method of claim 11 wherein embedding a plurality of nodes of the bipartite graph into a respective superconducting qubit includes embedding a plurality of nodes of the bipartite graph into a respective superconducting qubit comprising an elongate loop of superconducting material interrupted by at least one Josephson junction.

13. The method of claim 10 wherein embedding one or more edges of the bipartite graph into a respective coupling device comprises at least one of: ferromagnetic coupling, anti-ferromagnetic coupling, zero coupling, or transverse coupling a respective pair of qubits selected from the first and the second set of qubits in the plurality of subtopologies.

14. The method of claim 10 wherein embedding a bipartite graph includes embedding a complete graph.

15. A method of producing one or more solutions to a computational problem by an analog computer, the analog computer comprising a receiver, a pre-processing manager, a quantum processor, an evolution module, and a readout device, the quantum processor including a plurality of qubits and one or more coupling devices arranged to form a topology, the topology including a plurality of subtopologies of qubits and coupling devices, the plurality of subtopologies arranged in a grid, each subtopology of qubits respectively including a respective first set of qubits; a respective second set of qubits, each of of the qubits in the respective second set of qubits which crosses at least one of the qubits of the first set of qubits; a respective first set of coupling devices, each coupling device in the respective first set of coupling devices selectively operable to directly communicatively couple one of the qubits in the respective first set of qubits to one of the qubits in the respective second set of qubits, and the topology further including a second set of coupling devices, each coupling device in the second set of coupling devices selectively operable to communicatively couple one of the qubits in one of the plurality of subtopologies with one of the qubits in another of the plurality of subtopologies,
the method comprising:
receiving the computational problem by the receiver;
mapping the computational problem onto a topological representation by the pre-processing manager;
embedding the topological representation onto the quantum processor by the pre-processing manager;
evolving the quantum processor by the evolution module; and
reading out the one or more solutions by the readout device.

16. The method of claim 15 wherein embedding the topological representation onto the quantum processor by the pre-processing manager includes embedding a graph comprising a p

Assignees

• D Wave Systems Inc
• D•Wave Systems Inc

Inventors

• Bunyk Paul
• Maibaum Felix

Classifications

• G06F15/82

  data or demand driven · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G01R1/06755

  Material aspects · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title