Chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9403672-B2
Application number	US-201514819174-A
Country	US
Kind code	B2
Filing date	Aug 5, 2015
Priority date	Aug 11, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.

First claim

What is claimed is:

1. A method of manufacturing a chip package, comprising:
forming at least a bump on a lower surface of an interposer;
forming a first insulation layer to cover the lower surface and the bump;
forming at least a trench extending from the lower surface towards an upper surface of the interposer;
forming a polymer supporting adhesive layer surrounding the bump;
coupling the interposer and a semiconductor chip by the polymer supporting adhesive layer, the semiconductor chip having at least a sensing component and a conductive pad electrically connected to the sensing component, wherein the bump is connected to the conductive pad;
forming a via extending from the upper surface towards the lower surface, the via going through the bump to expose the conductive pad, wherein a width of the via is smaller than a width of the bump;
forming a second insulation layer covering the upper surface and a wall of the via;
forming a redistribution layer on the second insulation layer and in the via to electrically connect to the conductive pad;
etching the interposer to expose the upper surface; and
forming a packaging layer covering the redistribution layer, the packaging layer having a second opening to expose the trench.

2. The method of manufacturing the chip package of claim 1 , wherein the via is formed by laser drilling.

3. The method of manufacturing the chip package of claim 1 , wherein the width of the via is substantially the same as the width of the bump.

4. The method of manufacturing the chip package of claim 1 , wherein forming the polymer supporting adhesive layer surrounding the bump further comprises:
coating the polymer supporting adhesive layer on the lower surface; and
photolithography etching the polymer supporting adhesive layer to expose the bump.

5. The method of manufacturing the chip package of claim 1 , wherein in between coupling the interposer and a semiconductor chip by the polymer supporting adhesive layer and forming the via further comprises:
thinning the interposer from the upper surface towards the lower surface.

6. The method of manufacturing the chip package of claim 1 , wherein forming the packaging layer covering the redistribution layer further comprises:
coating the packaging layer on the upper surface and the redistribution layer; and
laser drilling the packaging layer to form the opening and expose the trench through the opening.

7. The method of manufacturing the chip package of claim 6 , wherein in coating the packaging layer on the redistribution layer, the packaging layer fills a portion of the via.

8. The method of manufacturing the chip package of claim 1 , wherein the polymer supporting adhesive layer comprises a thermal cured material, a UV light cured material or a combination thereof.

9. The method of manufacturing the chip package of claim 8 , wherein the thermal cured material includes epoxy.

10. The method of manufacturing the chip package of claim 1 , further comprising:
forming a soldering ball on the interposer, the soldering ball electrically connected to the redistribution layer.

11. The method of manufacturing the chip package of claim 1 , wherein the polymer supporting adhesive layer is a polymer dam.

12. A chip package, comprising:
a semiconductor chip having at least a sensing unit disposed in an active area and at least a conductive pad electrically connected to the sensing unit;
an interposer disposed on the semiconductor chip, the interposer having at least a trench and at least a via, wherein the trench goes through the interposer, and the via exposes the conductive pad;
a polymer supporting adhesive layer sandwiched in between the semiconductor chip and the interposer, the polymer supporting adhesive layer formed with a first opening connecting to the via to expose the conductive pad;
a first insulation layer disposed on a lower surface of the interposer and a portion of the first insulation layer disposed in the first opening to cover the polymer supporting adhesive layer;
a redistribution layer disposed on the interposer and in the via to electrically connect to the conductive pad; and
a packaging layer covering the interposer and the redistribution layer, the packaging layer formed with a second opening to expose the trench.

13. The chip package of claim 12 , wherein the polymer supporting adhesive layer includes a thermal cured material, a UV light cured material or a combination thereof.

14. The chip package of claim 13 , wherein the thermal cured material includes epoxy.

15. The chip package of claim 12 , wherein the sensing unit is disposed in an active area of the semiconductor chip, the conductive chip is disposed in a peripheral area of the semiconductor chip, and the peripheral area surrounds the active area.

16. The chip package of claim 15 , wherein a projection of the trench over the semiconductor chip is positioned over at least one side of the active area.

17. The chip package of claim 12 , wherein the packaging layer fills a portion of the via.

18. The chip package of claim 12 , further comprising a soldering ball disposed on the interposer, the soldering ball being electrically connected to the redistribution layer.

19. The chip package of claim 12 , further comprising a soldering wire electrically connected to the redistribution layer.

20. The chip package of claim 12 , further comprising a second insulation layer disposed on an upper surface of the interposer and a wall of the via.

21. The chip package of claim 20 , wherein the first insulation layer and the second insulation layer include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

22. The chip package of claim 12 , wherein the polymer supporting adhesive layer is a polymer dam.

Assignees

• Xintec Inc

Inventors

• Lin Chien-Min

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title