Test signal generator for sigma-delta ADC

Patent metadata

Field	Value
Publication number	US-9401728-B2
Application number	US-201514714946-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	Dec 16, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

The test signal generator generates an analog and digital test signals to test a sigma-delta ADC which has an analog portion succeeded by a digital decimation filter. The test signal generator supplies a first digital test signal having a first particular number of bits N and a first particular bit rate RN corresponding to digital signals occurring after the digital decimation filter. A digital sigma-delta modulator converts the first digital test signal into a second digital test signal having a second particular number of bits M<N thereby corresponding to a digital signal occurring at an input of the digital decimation filter. A DAC converts the second digital test signal into an analog signal, and a filter to filter the analog signal to obtain an analog test signal for testing the analog portion.

First claim

The invention claimed is:

1. A signal generator for generating an analog test signal, a first digital test signal and a second digital test signal to test a sigma-delta ADC comprising an analog portion for converting an analog input signal into a digital data stream and a digital portion comprising a digital decimation filter for processing the digital data stream into a digital output signal, the signal generator comprises:
a digital waveform generator arranged for supplying the first digital test signal to a first output of the signal generator, the first digital test signal having a first particular number of bits and a first particular bit rate corresponding to digital signals occurring after the digital decimation filter of the sigma-delta ADC, the digital waveform generator comprises a digital sigma-delta modulator coupled for converting the first digital test signal into the second digital test signal and for supplying the second digital test signal to a second output of the signal generator, the second digital test signal having a second particular number of bits being lower than the first particular number of bits thereby corresponding to a digital signal occurring at an input of the digital decimation filter of the sigma-delta ADC,
a first DAC being coupled to the digital sigma-delta modulator for converting the second digital test signal into an analog signal, and
a first analog filter coupled to the first DAC for filtering the analog signal to obtain the analog test signal at a third output of the signal generator for testing the analog portion of the sigma-delta ADC.

2. The signal generator as claimed in claim 1 , further comprising
a clock generator coupled to the digital waveform generator for supplying a clock signal to the digital waveform generator, and
a controller comprising a controller input for receiving an input control signal and being coupled to the clock generator for supplying a clock control signal to the clock generator to control a repetition frequency of the clock signal for obtaining the first particular bit rate to correspond to a bit rate of a digital signal occurring at an output of the digital decimation filter of the sigma-delta ADC and to the digital waveform generator, wherein the digital waveform generator is arranged for receiving the control signal to obtain the first particular number of bits to correspond to the number of bits of the digital signal occurring at the output of the digital decimation filter of the sigma-delta ADC.

3. The signal generator as claimed in claim 1 , wherein the digital sigma-delta modulator is arranged for supplying the second digital test signal having the second particular number of bits equal to a quantized signal in the sigma-delta ADC.

4. The signal generator as claimed in claim 1 , wherein the first DAC is a digital to analog converter for converting the quantized signal of a sigma-delta ADC into an analog quantized signal.

5. The signal generator as claimed in claim 1 , wherein the first analog filter is arranged for low-pass filtering of the analog signal supplied by the first DAC.

6. A system comprising the signal generator as claimed in claim 1 and the sigma-delta ADC to be tested, wherein the analog portion of the sigma-delta ADC to be tested comprises:
an input for receiving the analog input signal,
a subtractor coupled to the input and to an output of a second DAC for subtracting an analog quantized signal supplied by the second DAC from the analog input signal to obtain an analog difference signal,
a second analog filter coupled to the subtractor for filtering the analog difference signal into a filtered difference signal,
a second quantizer coupled to the second analog filter for receiving the filtered difference signal and being coupled to the second DAC for supplying a quantized signal being the digital data stream to the second DAC, and
the second DAC being arranged to convert the digital data stream into the analog quantized signal.

7. The system as claimed in claim 6 , wherein the sigma-delta ADC to be tested further comprises a first switch being arranged for coupling the analog input signal to the subtractor in a normal mode wherein the sigma-delta ADC to be tested is arranged for converting the analog input signal into the digital data stream, or for coupling the analog test signal to the subtractor in a test mode wherein the sigma-delta ADC to be tested is tested.

8. The system as claimed in claim 2 , wherein the sigma-delta ADC to be tested further comprises a first switch being arranged for coupling the analog input signal to the subtractor in a normal mode wherein the sigma-delta ADC to be tested is arranged for converting the analog input signal into the digital data stream, or for coupling the analog test signal to the subtractor in a test mode wherein the sigma-delta ADC to be tested is tested, and wherein the digital waveform generator is arranged for obtaining the second particular number of bits to correspond to the number of bits of the digital data stream.

9. The system as claimed in claim 2 , wherein the sigma-delta ADC to be tested further comprises a first switch being arranged for coupling the analog input signal to the subtractor in a normal mode wherein the sigma-delta ADC to be tested is arranged for converting the analog input signal into the digital data stream, or to coupling the analog test signal to the subtractor in a test mode wherein the sigma-delta ADC to be tested is tested, and wherein the digital portion of the sigma-delta ADC to be tested comprises a first decimation filter coupled for receiving the digital data stream to supply a first decimated digital data stream, and wherein the controller is arranged for controlling the clock generator to supply a repetition frequency of the clock signal for obtaining the first particular bit rate corresponding to a bit rate of the first decimated digital data stream, and for controlling the digital waveform generator to obtain the first particular number of bits corresponding to the number of bits of the first decimated digital data stream.

10. The system as claimed in claim 9 , wherein the digital portion of the sigma-delta ADC to be tested comprises a first multiplexer coupled to the second quantizer, the digital waveform generator and the first decimation filter for transferring the digital data stream to the first decimation filter when in normal mode and for transferring the first digital test signal to the first decimation filter when in test mode.

11. The system as claimed in claim 9 , wherein the digital portion of the sigma-delta ADC to be tested further comprises a second decimation filter arranged for converting the first decimated digital data stream into a second decimated digital data stream and wherein the controller is arranged for controlling the clock generator to supply a repetition frequency of the clock signal for obtaining the first particular bit rate corresponding to a bit rate of the second decimated digital data stream, and for controlling the digital waveform generator to obtain the first particular number of bits corresponding to the number of bits of the second decimated digital data stream.

12. The system as claimed in claim 11 , wherein the digital portion of the sigma-delta ADC to be tested comprises a second multiplexer coupled to the first decimation filter, the digital waveform generator and the second decimation filter 21 for transferring the first decimated digital data stream to the second decimation filter when in normal mode and for transferring the first digital test signal to the second decimation filter when in test mode.

13. The system as claimed in claim

Assignees

• Doare Olivier Vincent
• Hales Rex Kenton
• Freescale Semiconductor Inc

Inventors

• Doare Olivier Vincent
• Hales Rex Kenton

Classifications

• H03M3/378 Primary

  Testing · CPC title

• H03M3/39

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title