Method for manufacturing transistor and transistor

Patent metadata

Field	Value
Publication number	US-9401478-B2
Application number	US-201414178651-A
Country	US
Kind code	B2
Filing date	Feb 12, 2014
Priority date	Aug 15, 2011
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A method for manufacturing a transistor includes: forming a base film for supporting a catalyst for electroless plating; forming a resist layer having an opening portion corresponding to source and drain electrodes onto the base film; causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating; removing the resist layer; performing a second electroless plating on a surface of an electrode which is formed by the first electroless plating and forming the source and drain electrodes; and forming a semiconductor layer in contact with surfaces of the source and drain electrodes, the surfaces facing each other, wherein an energy level difference between a work function of a material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a material of the semiconductor layer is less than an energy level difference between a work function of a material which is used for the first electroless plating and the energy level of the molecular orbital.

First claim

What is claimed is:

1. A method for manufacturing a transistor, the method comprising:
forming a base film for supporting a catalyst for electroless plating;
forming a resist layer having an opening portion onto the base film, the opening portion having first and second openings corresponding to a source electrode and a drain electrode, respectively;
causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating to form electrodes respectively in the first and second openings;
removing the resist layer;
after the removing the resist layer, performing a second electroless plating on a surface of each of the electrodes formed by the first electroless plating, thereby forming a source electrode and a drain electrode; and
forming a semiconductor layer in contact with a surface of the source electrode and a surface of the drain electrode, the surfaces facing each other, wherein
an energy level difference between a work function of a metal material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a formation material of the semiconductor layer is less than an energy level difference between a work function of a metal material which is used for the first electroless plating and the energy level of the molecular orbital.

2. The method for manufacturing a transistor according to claim 1 , wherein
the semiconductor layer is constituted by an organic semiconductor.

3. The method for manufacturing a transistor according to claim 2 , wherein
a solution in which a formation material of the organic semiconductor is dissolved is placed, and the semiconductor layer is formed.

4. The method for manufacturing a transistor according to claim 1 , wherein
the base film includes: a base material constituted by a photo curable resin; and alumina particles of which an average particle size is 100 nm or less, wherein
the base film is selectively formed by placing a solution which includes a precursor of the base material and the alumina particles and selectively performing light irradiation.

5. The method for manufacturing a transistor according to claim 4 , wherein
the photo curable resin is an ultraviolet curable resin.

6. The method for manufacturing a transistor according to claim 1 , wherein
the transistor is formed on a substrate constituted by a non-metal material.

7. The method for manufacturing a transistor according to claim 1 , wherein
the transistor is formed on a substrate constituted by a resin material.

8. The method for manufacturing a transistor according to claim 7 , wherein
the substrate has flexibility.

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei
• Sugizaki Takashi
• Miyamoto Kenji

Classifications

• H01L51/0021 Primary

  Electricity · mapped topic

• H01L51/0558

  Electricity · mapped topic

• H01L51/0545

  Electricity · mapped topic

• H01L51/105

  Electricity · mapped topic

• H10K71/60 Primary

  Forming conductive regions or layers, e.g. electrodes · CPC title