Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9401417-B2
Application number	US-201514726595-A
Country	US
Kind code	B2
Filing date	May 31, 2015
Priority date	Jan 10, 2013
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate having at least a gate region and at least a source/drain region adjoining the gate region;
forming at least an epitaxial layer on the semiconductor substrate within the source/drain region;
forming a fluorine-containing layer on a surface of the epitaxial layer, whereby a top surface of the gate structure is not covered by the fluorine-containing layer during the step of forming the fluorine-containing layer;
forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer;
forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure;
forming at least a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer; and
forming at least a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole, wherein the fluorine-containing layer is disposed on a periphery of the metal silicide layer after the step of forming the metal silicide layer.

2. The method according to claim 1 , wherein the step of forming a fluorine-containing layer comprises a fluorine ion implantation process.

3. The method according to claim 1 , wherein the step of forming the fluorine-containing layer comprises:
forming an oxide film conformally covering the epitaxial layer; and
performing an etching process to remove the oxide film, wherein an etchant of the etching process comprises a fluorine-containing molecule.

4. The method according to claim 3 , wherein the oxide film is completely or partially removed through the etching process.

5. The method according to claim 1 , wherein the fluorine-containing layer is further located under a bottom of the metal silicide layer.

6. The method according to claim 1 , wherein a position of the fluorine-containing layer disposed on the periphery of the metal silicide layer is higher than a position of the fluorine-containing layer located under a bottom of the metal silicide layer.

7. The method according to claim 1 , wherein the metal gate structure further comprises a metal gate and at least a spacer disposed on a sidewall of the metal gate.

8. The method according to claim 7 , wherein the spacer has a single-layered structure or a multi-layered structure.

9. The method according to claim 1 , wherein the epitaxial layer comprises silicon germanium, silicon phosphorous, silicon carbon or phosphorus-doped silicon carbon.

10. The method according to claim 1 , wherein the metal silicide layer comprises nickel silicide, nickel platinum silicide, platinum silicide, cobalt silicide or tungsten silicide.

11. The method according to claim 1 , wherein the contact hole has an elliptical shape, a bar shape or a circular shape.

12. The method according to claim 1 , wherein the semiconductor device is a fin field effect transistor.

13. The method according to claim 1 , wherein the fluorine-containing layer encloses sides of the metal silicide layer.

14. The method according to claim 1 , further comprising depositing an etch stop film disposed on the fluorine-containing layer.

Assignees

• United Microelectronics Corp

Inventors

• Chen Yi-Wei
• Huang Chien-Chung
• Lew Kok Seen

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/076

  in via holes or trenches · CPC title