Junction overlap control in a semiconductor device using a sacrificial spacer layer
US-2015380514-A1 · Dec 31, 2015 · US
Method for reducing gate height variation due to overlapping masks
US9401416B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9401416-B2 |
| Application number | US-201414560035-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 4, 2014 |
| Priority date | Dec 4, 2014 |
| Publication date | Jul 26, 2016 |
| Grant date | Jul 26, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.
First claim
Opening claim text (preview).
What is claimed: 1. A method, comprising: forming a placeholder gate structure above a substrate, said placeholder gate structure comprising a placeholder material and a cap structure defined on a top surface of said placeholder material, said cap structure comprising a first cap layer disposed above said placeholder material and a second cap layer disposed above said first cap layer; performing an oxidization process on at least a portion of said second cap layer to form an oxi…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/024Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9401416B2 cover?
- A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first …
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/024. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).