Semiconductor device package with organic interposer

Patent metadata

Field	Value
Publication number	US-9401345-B2
Application number	US-201414474294-A
Country	US
Kind code	B2
Filing date	Sep 1, 2014
Priority date	Sep 1, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

First claim

The invention claimed is:

1. A method for assembling an integrated circuit package, the method comprising:
a) providing a flexible tape having first and second sets of bond pads on respective first and second surfaces thereof;
b) attaching the first surface of the flexible tape to a carrier;
c) forming conductive pillars on the second set of bond pads;
d) depositing an intermediate layer of polymeric compound on the second surface of the flexible tape;
e) grinding a surface of the intermediate layer to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer;
f) removing the carrier from the sub-assembly, thereby creating an interposer;
g) attaching the interposer to a substrate;
h) attaching at least one die to the interposer,
wherein, after step e) and before step f), the method further comprises:
attaching an additional flexible tape to the intermediate layer using an adhesive layer;
forming openings in the additional flexible tape and the adhesive layer, thereby uncovering the exposed ends of the conductive pillars;
depositing solder into the openings; and
reflowing the solder to form solder plugs that connect the conductive pillars to conductive traces on the additional flexible tape,
whereby the interposer includes the attached additional flexible tape; and

overmolding the at least one die, the interposer, and a portion of the substrate with a molding compound, thereby leaving a surface of the substrate exposed.

2. The method of claim 1 wherein the flexible tape has one or more conductive traces and one or more vias configured to interconnecting the first and second sets of bond pads.

3. The method of claim 1 wherein the second set of bond pads has a pitch greater than that of the first set of bond pads.

4. The method of claim 1 , wherein step c) comprises:
c1) depositing photoresist on the second surface of the flexible tape;
c2) patterning the photoresist to form openings in the photoresist that exposes the second set of bond pads;
c3) depositing metal into the openings to form the conductive pillars; and
c4) removing the patterned photoresist.

5. The method of claim 4 wherein, in step c3), the metal is deposited by plating copper or solder into the openings.

6. The method of claim 1 wherein, in step c), the metal is deposited by forming wire bond stud bumps or by placing solder balls onto the second set of bond pads.

7. The method of claim 1 , wherein a laser is used to form the openings in the additional flexible tape and the adhesive layer.

8. The method of claim 7 , wherein the additional flexible tape has bond pads on a surface thereof and the substrate has bond pads on a surface thereof, the method further comprising:
forming metal balls on the additional flexible tape bond pads or the substrate bond pads; and
ball-bonding the substrate bond pads to the additional flexible tape bond pads;
wherein the additional flexible tape bond pads are aligned with the substrate bond pads.

9. The method of claim 1 , wherein step h) comprises:
forming metal balls on die bond pads on the at least one die; and
flip-chip bonding the at least one die to the interposer,
wherein the die bond pads are aligned with the first set of bond pads on the flexible tape.

10. The method of claim 1 , wherein the substrate has bond pads on first and second surfaces thereof, the method further comprising:
forming metal balls on the bond pads on the first surface of the substrate or the exposed ends of the conductive pillars;
ball-bonding the exposed ends of the conductive pillars to corresponding bond pads on the first surface of the substrate;
wherein the bond pads on the first surface of the substrate are aligned with the exposed ends of the conductive pillars.

11. The method of claim 10 , further comprising:
attaching solder balls to the bond pads on the second surface of the substrate;
wherein the bond pads on the second surface of the substrate are arranged in rows and columns along a periphery of the substrate.

12. The method of claim 1 , wherein the molding compound and the polymeric compound comprise epoxy.

13. The method of claim 1 , further comprising:
backgrinding the overmold to expose a backside of the at least one die; and
attaching a heat spreader to the exposed backside of the at least one die.

14. The method of claim 1 , wherein step a) comprises:
a1) providing a flexible dielectric layer;
a2) depositing a first conductive layer on the dielectric layer to form the first surface of the flexible tape;
a3) depositing a second conductive layer on the dielectric layer opposite the first conductive layer to form the second surface of the flexible tape;
a4) patterning the first conductive layer to form first conductive traces and the first set of bond pads;
a5) patterning the second conductive layer to form second conductive traces and the second set of bond pads; and
a6) forming conductive vias in the dielectric layer, the conductive vias configured to electrically interconnect the first and second conductive traces.

Assignees

• Foong Chee Seng
• Kalandar Navas Khan Oratti
• Tan Lan Chu
• Freescale Semiconductor Inc

Inventors

• Foong Chee Seng
• Kalandar Navas Khan Oratti
• Tan Lan Chu

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title