Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9401331B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9401331-B2 |
| Application number | US-201414267800-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 1, 2014 |
| Priority date | Dec 12, 2008 |
| Publication date | Jul 26, 2016 |
| Grant date | Jul 26, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
First claim
Opening claim text (preview).
What is claimed: 1. A method of making a semiconductor device, comprising: providing a first conductive layer; forming a conductive pillar over a first surface of a first portion of the first conductive layer; disposing a semiconductor die over the first surface of a second portion of the first conductive layer; and forming a bump over a second surface of the first conductive layer opposite the first surface of the conductive layer to contact the first portion of the first c…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9401331B2 cover?
- A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is …
- Who is the assignee on this patent?
- Stats Chippac Ltd, Stats Chippac Pte Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).