Aggregation of semiconductor devices and the method thereof

Patent metadata

Field	Value
Publication number	US-9397275-B2
Application number	US-201514663439-A
Country	US
Kind code	B2
Filing date	Mar 19, 2015
Priority date	Jul 26, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of manufacturing an aggregation of semiconductor devices comprising the steps of providing a first layer; sequentially addressing and adhering a plurality of semiconductor devices to the first layer to form a shape having a curve; providing a second layer; and adhering the second layer to the first layer.

First claim

What is claimed is:

1. A method of manufacturing an aggregation of semiconductor devices comprising the steps:
providing a first layer;
sequentially addressing and adhering a plurality of semiconductor devices to the first layer to form a shape having a curve;
providing a second layer; and
adhering the second layer to the first layer, wherein the first layer is capable of being expanded to over 2 times of the original area size of the first layer.

2. The method according to claim 1 , wherein the first layer comprises an adhesive glue layer and the plurality of semiconductor devices are adhered on the adhesive glue layer.

3. The method according to claim 1 , wherein the plurality of the semiconductor devices is sequentially addressed and adhered to the first layer from column to column.

4. The method according to claim 1 , wherein the plurality of the semiconductor devices is sequentially addressed and adhered to the adhesive glue layer by a sorter.

5. The method according to claim 2 , wherein the second layer adheres to the first layer by the adhesive glue layer and covers the plurality of semiconductor devices.

6. The method according to claim 1 , wherein the shape comprises a circle or a regular polygon with a number of sides thereof being greater than 4.

7. The method according to claim 1 , wherein the plurality of semiconductor devices forms an arrangement at a center of the aggregation.

8. The method according to claim 1 , further comprising testing the plurality of semiconductor devices to get a testing result by a tester before the step of sequentially addressing and adhering a plurality of semiconductor devices to the first layer.

9. The method according to claim 8 , wherein the sorter comprises a predetermined bin structure defining a variety of bin codes, and the plurality of semiconductor devices arranged on the first layer have the same bin code.

10. The method according to claim 9 , wherein the predetermined bin structure comprises an electrical or luminous characteristic.

11. The method according to claim 1 , wherein the plurality of semiconductor devices comprises an LED chip or a photovoltaic chip.

12. The method according to claim 1 , wherein the shape has a flat side.

13. The method according to claim 1 , further comprises forming a tag on a corner of the first layer.

14. The method according to claim 1 , wherein the shape is approximately a circle.

15. The method according to claim 1 , wherein a distance between any two points of the shape is not greater than 15 cm.

16. The method according to claim 1 , wherein each of the plurality of semiconductor devices further comprises a conductive pad.

17. The method according to claim 1 , wherein the semiconductor devices are aligned to each other.

18. The method according to claim 1 , wherein a distance between adjacent two of the semiconductor devices is between 50 μm and 5 mm.

19. The method according to claim 12 , wherein the step of sequentially addressing and adhering the plurality of semiconductor devices to the first layer is started from the flat side.

Assignees

• Epistar Corp

Inventors

• Lin Hsu-Cheng
• Chiu Ching-Yi
• Fang Pei-Shan
• Chen Chun-Chang

Classifications

• H10P72/7428

  used to support diced chips prior to mounting · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title