Thin film transistor, manufacturing method thereof and thin film transistor array substrate

Patent metadata

Field	Value
Publication number	US-9397221-B2
Application number	US-201314235063-A
Country	US
Kind code	B2
Filing date	Dec 5, 2013
Priority date	Nov 29, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

The present invention discloses a thin film transistor, comprising an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode formed on a substrate. The active layer is above the substrate. The gate insulating layer, the source electrode, and the drain electrode are above the active layer. The gate electrode is above the gate insulating layer. Wherein, the thin film transistor further comprises a shielding layer between the substrate and the active layer, the shielding layer is used to absorb external light. The thin film transistor according to the present invention not only has strong stability, but also has high output efficiency. Moreover, the thin film transistor can follow the existing process, which facilitates mass production. The present invention further discloses a manufacturing method of the thin film transistor and a thin film transistor array substrate using the thin film transistor.

First claim

What is claimed is:

1. A manufacturing method of thin film transistor, comprising the following steps:
A. forming a shielding layer on a substrate;
B. forming an active layer on the shielding layer;
C. forming a gate insulating layer on the active layer, and patterning the gate insulating layer, so that a first zone and a second zone of the active layer are exposed;
D. forming a gate electrode on the gate insulating layer;
E. forming a passivation layer on the substrate, the first zone, the second zone, and a gate electrode, and pattering the passivation layer, so that the first zone and the second zone are exposed;
F. forming a source electrode and a drain electrode on the passivation layer, and the source electrode and the drain electrode respectively contacting with the first zone and the second zone; and
wherein a ratio of using gases as depositing the gate insulating layer is SiH 4 /N 2 O<1/65, and the ratio of using gases as depositing the passivation layer is SiH 4 /N 2 O>1/50.

2. The manufacturing method as claimed in claim 1 , wherein the specific implementation of forming a shielding layer on a substrate in the step A is:
A1. forming a metal layer on the substrate;
A2. forming an insulating layer on the metal layer.

3. The manufacturing method as claimed in claim 1 , wherein the material of the active layer is indium gallium zinc oxide.

4. The manufacturing method as claimed in claim 2 , wherein the material of the active layer is indium gallium zinc oxide.

5. The manufacturing method as claimed in claim 3 , wherein the first zone of the active layer and the second zone are n-type heavily doped region.

6. The manufacturing method as claimed in claim 4 , wherein the first zone of the active layer and the second zone are n-type heavily doped region.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Su Chih-Yu

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D62/875

  being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title