Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices

Patent metadata

Field	Value
Publication number	US-9397219-B2
Application number	US-201514680458-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Jul 25, 2014
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a channel region;
a pair of source/drain regions on the substrate on opposite sides of the channel region; and
a gate structure on an upper surface of the channel region, the gate structure including a gate electrode pattern and a gate dielectric layer that is between the channel region and the gate electrode pattern, and a gate spacer that covers respective lateral surfaces of the gate electrode pattern and the gate dielectric layer,
wherein
at least one of the pair of source/drain regions comprises a first strain-inducing layer and a second strain-inducing layer, and
wherein a portion of the first strain-inducing layer that is beneath the upper surface of the channel region is between a lateral surface of the channel region and the second strain-inducing layer and directly contacts the gate dielectric layer.

2. The semiconductor device of claim 1 , wherein the first strain-inducing layer also extends between a lower surface of the second strain-inducing layer and the substrate.

3. The semiconductor device of claim 2 , wherein a thickness of a portion of the first strain-inducing layer that is between the second strain-inducing layer and the lateral surface of the channel region is less than a thickness of a portion of the first strain-inducing layer that is between the lower surface of the second strain-inducing layer and the substrate.

4. The semiconductor device of claim 1 , wherein the second strain-inducing layer directly contacts a portion of a lower surface of the gate spacer.

5. The semiconductor device of claim 1 , wherein a doping concentration of the first strain-inducing layer is less than a doping concentration of the second strain-inducing layer.

6. The semiconductor device of claim 5 , wherein the second strain-inducing layer and the channel region have a first conductivity type and a second conductivity type, respectively, that are different, and the first strain-inducing layer is substantially un-doped.

7. The semiconductor device of claim 1 , further comprising a third strain-inducing layer that is between the first strain-inducing layer and the second strain-inducing layer,
wherein
the first, second, and third strain-inducing layers have respective first, second, and third germanium (Ge) contents, and
the third Ge content is smaller than at least one of the first Ge content and the second Ge content.

8. The semiconductor device of claim 7 , wherein
the first, second, and third strain-inducing layers have respective first, second, and third doping concentrations, and
the first doping concentration is smaller than at least one of the second doping concentration and the third doping concentration.

9. The semiconductor device of claim 8 , wherein the third doping concentration is smaller than the second doping concentration.

10. The semiconductor device of claim 1 , wherein the first strain-inducing layer directly contacts a lower surface of the gate spacer and a lower surface of the gate dielectric layer.

11. The semiconductor device of claim 1 , wherein a first portion of the gate dielectric layer is between the channel region and the gate electrode pattern and a second portion of the gate dielectric layer is between the gate electrode pattern and the gate spacer.

12. The semiconductor device of claim 1 , wherein
a fin structure comprising the channel region and a pair of recesses that are on both sides of the channel region is on the substrate, and
the pair of source/drain regions are in the pair of recesses.

13. A strain transistor comprising:
a substrate comprising a channel region and a pair of recesses on opposing sides of the channel region;
a gate structure on the channel region that includes a gate electrode pattern, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer that covers respective lateral surfaces of the gate electrode pattern and the gate dielectric layer; and
a pair of source/drain regions formed in the pair of recesses, respectively,
wherein
at least one of the pair of source/drain regions comprises a first semiconductor strain-inducing layer and a second semiconductor strain-inducing layer, and
the first semiconductor strain-inducing layer is between the second semiconductor strain-inducing layer and a lateral surface of the channel region and directly contacts the gate spacer and the gate dielectric layer.

14. The strain transistor of claim 13 , wherein the first semiconductor strain-inducing layer also is between the second semiconductor strain-inducing layer and a bottom of each of the recesses.

15. The strain transistor of claim 13 , further comprising a third semiconductor strain-inducing layer that is between the first semiconductor strain-inducing layer and the second semiconductor strain-inducing layer, the third semiconductor strain-inducing layer having a Ge content that is smaller than a Ge content of at least one of the first and second semiconductor strain-inducing layers.

16. The strain transistor of claim 15 , wherein
the first, second, and third semiconductor strain-inducing layers have respective first, second, and third doping concentrations, and
the first doping concentration is smaller than the third doping concentration, and the third doping concentration is smaller than the second doping concentration.

17. The strain transistor of claim 13 , wherein
the second semiconductor strain-inducing layer and the channel region have a first conductivity type and a second conductivity type, respectively, which are different, and
the first semiconductor strain-inducing layer has a first conductivity type with a doping concentration that is smaller than a doping concentration of the second semiconductor strain-inducing layer.

18. A semiconductor device comprising:
a substrate;
a fin structure on the substrate, the fin structure comprising a pair of channel regions that are separated by a recess;
a pair of gate structures on the respective pair of channel regions, each gate structure comprising a gate electrode pattern that extends to intersect the fin structure, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer that covers respective lateral surfaces of the gate electrode pattern and the gate dielectric layer; and
a source/drain region extending upwardly from the recess,
wherein
the source/drain region comprises a first strain-inducing layer and a second strain-inducing layer that cover respective lateral surfaces of the pair of the channel regions that face each other and the bottom of the recess, and
the first strain-inducing layer is between each of the respective lateral surfaces of the channel regions that face each other and the second strain-inducing layer and directly contacts a boundary between the gate spacer and the gate dielectric layer on a lower surface of each of the pair of gate structures.

19. The semiconductor device of claim 18 , wherein the first strain-inducing layer is also between the second strain-inducing layer and the bottom of the recess.

20. The semiconductor device of claim 18 , wherein
the first and second strain-inducing layers have respective first and second doping concentrations of a first conductivity type dopant, and
the first doping concentration is smaller than the second doping concentration.

Assignees

• Kim Seok-Hoon
• Kim Jin-Bum
• Lee Kwan-Heum
• Lee Byeong-Chan
• Lee Cho-Eun
• Jung Su-Jin
• Samsung Electronics Co Ltd

Inventors

• Kim Seok-Hoon
• Kim Jin-Bum
• Lee Kwan-Heum
• Lee Byeong-Chan
• Lee Cho-Eun
• Jung Su-Jin

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title