Active regions with compatible dielectric layers

Patent metadata

Field	Value
Publication number	US-9397165-B2
Application number	US-201615018408-A
Country	US
Kind code	B2
Filing date	Feb 8, 2016
Priority date	Sep 18, 2006
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a crystalline silicon substrate;
a germanium region disposed within the silicon substrate;
a silicon oxide gate dielectric layer disposed directly on the germanium region;
a metal gate electrode disposed above the silicon oxide gate dielectric layer;
a pair of dielectric sidewall spacers adjacent the gate electrode;
a high-k gate dielectric layer disposed on the silicon oxide gate dielectric layer directly between the silicon oxide gate dielectric layer and the metal gate electrode, and disposed along sidewalls of the pair of dielectric sidewall spacers directly between the pair of dielectric sidewall spacers and the metal gate electrode;
a pair of source/drain regions disposed in the germanium region on either side of the gate electrode; and
a channel region disposed in the germanium region between the pair of source/drain regions.

2. The semiconductor device of claim 1 , further comprising:
a pair of isolation regions disposed in the crystalline silicon substrate on either side of the germanium region.

3. The semiconductor device of claim 2 , wherein the pair of isolation regions extend to a depth in the crystalline silicon substrate below a bottommost surface of the germanium region.

4. The semiconductor device of claim 1 , further comprising:
a pair of tip regions disposed in the germanium region on either side of the channel region, between the channel region and the pair of source/drain regions.

5. The semiconductor device of claim 1 , wherein the high-k gate dielectric layer is hafnium oxide.

6. The semiconductor device of claim 1 , wherein the source/drain regions are raised source/drain regions having an uppermost surface above an uppermost surface of the germanium region.

7. The semiconductor device of claim 6 , wherein the source/drain regions have a lattice constant different than the germanium region.

8. A semiconductor device, comprising:
a crystalline silicon substrate;
a group III-V material region disposed within the silicon substrate;
a silicon oxide gate dielectric layer disposed directly on the group III-V material region;
a metal gate electrode disposed above the silicon oxide gate dielectric layer;
a pair of dielectric sidewall spacers adjacent the gate electrode;
a high-k gate dielectric layer disposed on the silicon oxide gate dielectric layer directly between the silicon oxide gate dielectric layer and the metal gate electrode, and disposed along sidewalls of the pair of dielectric sidewall spacers directly between the pair of dielectric sidewall spacers and the metal gate electrode;
a pair of source/drain regions disposed in the group III-V material region on either side of the gate electrode; and
a channel region disposed in the group III-V material region between the pair of source/drain regions.

9. The semiconductor device of claim 8 , further comprising:
a pair of isolation regions disposed in the crystalline silicon substrate on either side of the group III-V material region.

10. The semiconductor device of claim 9 , wherein the pair of isolation regions extend to a depth in the crystalline silicon substrate below a bottommost surface of the group III-V material region.

11. The semiconductor device of claim 8 , further comprising:
a pair of tip regions disposed in the group III-V material region on either side of the channel region, between the channel region and the pair of source/drain regions.

12. The semiconductor device of claim 8 , wherein the high-k gate dielectric layer is hafnium oxide.

13. The semiconductor device of claim 8 , wherein the source/drain regions are raised source/drain regions having an uppermost surface above an uppermost surface of the group III-V material region.

14. The semiconductor device of claim 13 , wherein the source/drain regions have a lattice constant different than the group III-V material region.

15. A non-planar semiconductor device, comprising:
a crystalline silicon lower fin portion;
a germanium upper fin portion disposed on the crystalline silicon lower fin portion;
a silicon oxide gate dielectric layer disposed directly on the germanium upper fin portion;
a metal gate electrode disposed above the silicon oxide gate dielectric layer;
a pair of dielectric sidewall spacers adjacent the gate electrode;
a high-k gate dielectric layer disposed on the silicon oxide gate dielectric layer directly between the silicon oxide gate dielectric layer and the metal gate electrode, and disposed along sidewalls of the pair of dielectric sidewall spacers directly between the pair of dielectric sidewall spacers and the metal gate electrode;
a pair of source/drain regions disposed in the germanium upper fin portion on either side of the gate electrode; and
a channel region disposed in the germanium upper fin portion between the pair of source/drain regions.

16. The non-planar semiconductor device of claim 15 , further comprising:
a pair of isolation regions disposed laterally adjacent to the crystalline silicon lower fin portion.

17. The non-planar semiconductor device of claim 15 , wherein the high-k gate dielectric layer is hafnium oxide.

18. A non-planar semiconductor device, comprising:
a crystalline silicon lower fin portion;
a group III-V material upper fin portion disposed on the crystalline silicon lower fin portion;
a silicon oxide gate dielectric layer disposed directly on the group III-V material upper fin portion;
a metal gate electrode disposed above the silicon oxide gate dielectric layer;
a pair of dielectric sidewall spacers adjacent the gate electrode;
a high-k gate dielectric layer disposed on the silicon oxide gate dielectric layer directly between the silicon oxide gate dielectric layer and the metal gate electrode, and disposed along sidewalls of the pair of dielectric sidewall spacers directly between the pair of dielectric sidewall spacers and the metal gate electrode;
a pair of source/drain regions disposed in the group III-V material upper fin portion on either side of the gate electrode; and
a channel region disposed in the group III-V material upper fin portion between the pair of source/drain regions.

19. The non-planar semiconductor device of claim 18 , further comprising:
a pair of isolation regions disposed laterally adjacent to the crystalline silicon lower fin portion.

20. The non-planar semiconductor device of claim 18 , wherein the high-k gate dielectric layer is hafnium oxide.

Assignees

• Ranade Pushkar
• Intel Corp

Inventors

• Ranade Pushkar

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P14/69398

  the material having a perovskite structure, e.g. BaTiO3 · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title