Non-volatile semiconductor memory device

US9397144B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9397144-B2
Application numberUS-201414483954-A
CountryUS
Kind codeB2
Filing dateSep 11, 2014
Priority dateFeb 26, 2010
Publication dateJul 19, 2016
Grant dateJul 19, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.

First claim

Opening claim text (preview).

What is claimed is: 1. A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of first lines arranged side by side in a first plane approximately vertical to a surface of the semiconductor substrate, each of the plurality of first lines extending along the surface of the semiconductor substrate; a plurality of second lines arranged side by side in a second plane along the first plane, each of the plurality of second lines extending approx…

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What does patent US9397144B2 cover?
According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance ch…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H01L27/2481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).