Liner for phase change memory (PCM) array and associated techniques and configurations

Patent metadata

Field	Value
Publication number	US-9397143-B2
Application number	US-201314137864-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a substrate, an array of phase change memory (PCM) elements disposed on the substrate, wherein individual PCM elements of the array of PCM elements comprise a chalcogenide material and a liner disposed on sidewall surfaces of the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O). Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method, comprising:
providing a substrate;
disposing a wordline layer on the substrate;
forming an array of phase change memory (PCM) elements directly on the wordline layer, wherein individual PCM elements of the array of PCM elements include an electrode layer directly coupled to the wordline layer and a chalcogenide material layer directly coupled to the electrode layer; and
forming a liner directly on sidewall surfaces of the individual PCM elements and directly on the wordline layer between the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O), the liner having a dielectric constant below a threshold, to reduce parasitic leakage associated with the wordline layer, wherein forming the liner includes depositing the liner by atomic layer deposition (ALD) at a temperature less than 250° C. to prevent damaging the chalcogenide material layer, including controlling Si content of the liner by adjusting an ALD cycle ratio n to m to prevent accumulating —Si—O—Si— and —O—Si—H groups on a surface of the liner during forming of the liner, wherein n represents a number of trimethyl aluminum/purge/H 2 O/purge cycles, and m represents a number of tris-dimethyalamine silane/purge/H 2 O/purge cycles, wherein a ratio of n to m is approximately 1 to 3.

2. The method of claim 1 , wherein:
forming the liner further includes depositing aluminum silicon oxide, wherein the liner comprises aluminum silicon oxide (Al x Si y O); and
x and y represent relative quantities of Al, Si and O, respectively.

3. The method of claim 1 , wherein:
forming the liner comprises depositing a material comprising Al, Si and O directly on the chalcogenide material; and
depositing the material covers the sidewall surfaces entirely with a substantially uniform thickness of the material.

4. The method of claim 3 , wherein depositing the material covers top surfaces of the individual PCM elements.

5. The method of claim 1 , wherein forming the array of PCM elements comprises:
depositing the electrode layer comprising carbon on the wordline layer disposed on the substrate;
depositing the chalcogenide material layer comprising a first chalcogenide material on the electrode layer;
depositing a third layer comprising carbon on the chalcogenide material layer;
depositing a fourth layer comprising a second chalcogenide material on the third layer; and
depositing a fifth layer comprising carbon on the fourth layer.

6. The method of claim 1 , further comprising:
depositing a seed layer on the liner.

7. The method of claim 6 , further comprising:
depositing a fill material on the seed layer to fill regions between the individual PCM elements.

Assignees

• Intel Corp

Inventors

• Rocklein Noel
• Tao Qian
• Song Zhe
• Bhat Vishwanath

Classifications

• H01L27/2481 Primary

  Electricity · mapped topic

• H01L45/141

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic