Hybrid high-k first and high-k last replacement gate process

Patent metadata

Field	Value
Publication number	US-9397100-B2
Application number	US-201414578732-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 29, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

First claim

What is claimed is:

1. A process of forming an integrated circuit, comprising the steps:
providing a partially processed wafer of the integrated circuit;
growing a high quality first gate dielectric on the partially processed wafer at a temperature of 850° C. or greater;
depositing a high-k first gate dielectric on the high quality first gate dielectric;
forming an NMOS polysilicon replacement gate of a replacement gate NMOS transistor on the high-k first gate dielectric;…

Assignees

• Texas Instruments Inc

Inventors

• Niimi Hiroaki
• Mehrotra Manoj
• Nandakumar Mahalingam

Classifications

• H10D64/01352

  Electricity · mapped topic

• H10D64/01344

  Electricity · mapped topic

• H10P95/064

  Electricity · mapped topic

• H10P95/062

  Electricity · mapped topic

• H10P76/204

  Electricity · mapped topic