Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit

Patent metadata

Field	Value
Publication number	US-9397018-B2
Application number	US-201313742456-A
Country	US
Kind code	B2
Filing date	Jan 16, 2013
Priority date	Jan 16, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an electrically conductive carrier;
a chip mounted on a top side of the carrier;
encapsulation material at least partially covering the chip and the carrier;
at least one interconnect disposed within the encapsulation material electrically connecting the chip to the carrier;
a layer stack disposed over the carrier on a bottom side of the carrier opposite the top side of the carrier, the layer stack comprising:
a plurality of discrete polymer layers, wherein at least one of the polymer layers is disposed over the carrier and disposed on at least a portion of a bottom side of the encapsulation material; and
one or more discrete ceramic layers, wherein at least one of the ceramic layers is disposed between a pair of the plurality of the polymer layers;
wherein a first layer and a last layer of the layer stack is each a polymer layer; wherein the first layer of the layer stack is connected to the last layer of the polymer stack so that the first layer and the second layer wrap around the layer stack;

wherein the carrier comprises an extension so that the encapsulation material and the layer stack do not cover any surface of the carrier extension.

2. The integrated circuit of claim 1 ,
wherein at least one of the polymer layers has a thickness ranging from about 200 μm to about 500 μm.

3. The integrated circuit of claim 1 ,
wherein at least one of the polymer layer comprises at least one material from the following group of materials, the group of materials consisting of: polyimide, epoxy, acrylate, silicone, Polyethylene terephthalate, Polyphenylensulfide, Polyetherimide, Polysulfone, Liquid Crystalline Polymers, Polyamideimide and Polyphenyloxide.

4. The integrated circuit of claim 1 ,
wherein the at least one ceramic layer comprises at least one from the following group of materials, the group of materials consisting of: calcium oxide, aluminum oxide, silicon oxide, aluminum nitride, and zirconium oxide, boron nitride, a metal oxide, a metal nitride, a metal carbide, a metal boron.

5. The integrated circuit of claim 1 ,
wherein each of the polymer layers is different from the encapsulation material.

6. The integrated circuit of claim 1 ,
wherein each of the polymer layers has a different coefficient of thermal expansion from the encapsulation material.

7. The integrated circuit of claim 1 ,
wherein the one or more ceramic layers comprise a low temperature co-fired ceramic.

8. The integrated circuit of claim 1 ,
wherein the one or more ceramic layers comprise ceramic particles embedded in a polymer material.

9. The integrated circuit of claim 1 ,
wherein the polymer material of the at least one ceramic layer is different from a polymer material of each of the plurality of polymer layers.

10. The integrated circuit of claim 1 , wherein a portion of the encapsulation material is formed on the carrier bottom side, the integrated circuit further comprising a further encapsulation material disposed on the carrier bottom side separate from the portion of the encapsulation material is formed on the carrier bottom side, wherein a top surface of the layer stack facing the carrier is disposed on the carrier bottom side, on the further encapsulation material and on the portion of the encapsulation material formed on the carrier bottom side.

11. The integrated circuit of claim 10 , wherein a portion of the carrier bottom side on which the layer stack is disposed is located laterally between the further encapsulation material and the portion of the encapsulation material formed on the carrier bottom side.

12. The integrated circuit of claim 1 , wherein the interconnect is connected to a side of the chip facing away from the carrier and to the top side of the carrier.

13. The integrated circuit of claim 12 , wherein the interconnect is bond wire.

14. The integrated circuit of claim 1 , wherein the surfaces of the carrier extension are exposed.

15. The integrated circuit of claim 1 , wherein the surfaces of the carrier extension are plated.

16. The integrated circuit of claim 1 , where an entire top surface of the carrier extension and an entire bottom surface of the carrier extension are respectively coplanar with the top side and the bottom side of the carrier.

17. An integrated circuit, comprising:
an electrically conductive carrier;
a chip mounted on a top side of the carrier;
encapsulation material at least partially covering the chip and the carrier;
at least one interconnect disposed within the encapsulation material electrically connecting the chip to the carrier;
a layer stack disposed over the carrier on a bottom side of the carrier opposite the top side of the carrier, the layer stack comprising:
a plurality of discrete polymer layers, wherein at least one of the polymer layers is disposed over the carrier and disposed on at least a portion of a bottom side of the encapsulation material; and
one or more discrete ceramic layers, wherein at least one of the ceramic layers is disposed between a pair of the plurality of the polymer layers;

wherein the carrier comprises an extension so that the encapsulation material and the layer stack do not cover any surface of the carrier extension;
wherein a portion of the encapsulation material is formed on the carrier bottom side, the integrated circuit further comprising a further encapsulation material disposed on the carrier bottom side separate from the portion of the encapsulation material is formed on the carrier bottom side, wherein a top surface of the layer stack facing the carrier is disposed on the carrier bottom side, on the further encapsulation material and on the portion of the encapsulation material formed on the carrier bottom side.

Assignees

• Infineon Technologies Ag

Inventors

• Otremba Ralf
• Hoeglauer Josef
• Schredl Juergen
• Schloegel Xaver
• Hable Wolfram
• Mengel Manfred
• Mahler Joachim
• Hosseini Khalil

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W76/17

  characterised by their materials · CPC title