System and method for mitigating oxide growth in a gate dielectric

Patent metadata

Field	Value
Publication number	US-9396951-B2
Application number	US-201514858422-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	May 13, 2003
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

First claim

What is claimed is:

1. A transistor device having a gate dielectric, a gate electrode, a source region and a drain region, wherein the gate dielectric is formed by a process comprising the steps of:
forming a dielectric layer on a substrate in a first process chamber of a processing system, the first process chamber having a first pumping element configured to evacuate gas from the first process chamber;
introducing nitrogen atoms in the dielectric layer using a plasma process in a second process chamber of the processing system, the second process chamber having a second pumping element configured to evacuate gas from the second process chamber;
performing a thermal process in a third process chamber;
transferring the substrate between the first process chamber, the second process chamber, and the third process chamber through a transfer chamber of the processing system, wherein the transfer chamber is connected to the first process chamber via a first vacuum lock door and connected the second process chamber via a second vacuum lock door, the transfer chamber having a gas distribution system and a third, distinct pumping element that maintain a pressure of about 3 Torr in the transfer chamber and actively purge the transfer chamber by flowing N 2 at a rate of 2 liters per minute to 7 liters per minute during the transferring of the substrate between the first process chamber, the second process chamber, and the third process chamber; and
introducing the substrate to the processing system through a load lock distinct from said transfer chamber to allow introduction and removal of the substrate from the processing system.

2. The transistor device of claim 1 , wherein the nitrogen atoms are introduced into a top surface of the dielectric layer by flowing N 2 in the plasma process having a power of 2W to 3000 W and a pressure of 5 mTorr to 50T.

3. The transistor device of claim 1 , wherein forming the dielectric layer comprises performing an in-situ steam generation (ISSG) process at a pressure of 1 Torr to 20 Torr.

4. The transistor device of claim 3 , wherein a temperature of the first process chamber is maintained at temperature of 500° C. to 700° C. prior to formation of the dielectric layer and 850° to 1050° C. during the formation of the dielectric layer.

5. The transistor device of claim 1 , wherein the step of performing the thermal process uses O 2 and a temperature of 400° C. to 1200° C.

6. The transistor device of claim 1 , wherein the step of performing the thermal process uses NO and a temperature of 400° C. to 1200° C.

7. The transistor device of claim 1 , wherein the gate electrode is formed by a process comprising the step of depositing a polysilicon layer over the dielectric layer in a fourth process chamber connected to the transfer chamber, wherein the substrate is transferred through the transfer chamber to the fourth process chamber while the gas distribution system and the third pumping element maintain a pressure of about 3 Torr to about 20 Torr in the transfer chamber and actively purge the transfer chamber by flowing N 2 at a rate of 2 liters per minute to 7 liters per minute.

8. The transistor device of claim 1 , wherein the first pumping element provides a pressure of 1 Torr to 20 Torr in the first process chamber during the step of forming the dielectric layer, the second pumping element provides a pressure of 5 mTorr to 50 Torr in the second process chamber during the step of introducing the nitrogen atoms, and a fourth pumping element provides a pressure of 0.5 Torr to 50 Torr in the third processing chamber during the step of performing the thermal process.

9. A transistor device having a gate dielectric, a gate electrode, a source region and a drain region, wherein the transistor device is formed by a process comprising the steps of:
forming a gate dielectric structure on the substrate using at least two sequential process steps:
wherein one step of the at least two sequential process steps forms a gate dielectric layer in a first process chamber of a processing system, the first process chamber having a first pumping element configured to evacuate gas from the first process chamber; and
wherein another step of the at least two sequential process steps is performed on the substrate in a second process chamber;

transferring the substrate between the first process chamber and the second process chamber through a transfer chamber of the processing system, wherein the transfer chamber is connected to the first process chamber via a first vacuum lock door and connected the second process chamber via a second vacuum lock door, the transfer chamber having a gas distribution system and a second, distinct pumping element that maintain a pressure of less than 760 Torr in the transfer chamber and actively purge the transfer chamber by flowing N 2 at a rate of 2 liters per minute to 7 liters per minute during the transferring of the substrate between the first process chamber and the second process chamber; and
introducing the substrate to the processing system through a load lock distinct from said transfer chamber to allow introduction and removal of the substrate from the processing system.

10. The transistor device of claim 9 , wherein the another step introduces nitrogen atoms into a top surface of the dielectric layer using a plasma process.

11. The transistor device of claim 9 , wherein the another step introduces nitrogen atoms into a top surface of the dielectric layer by flowing N 2 in a plasma process having a power of 2W to 3000 W and a pressure of 5 mTorr to 50T.

12. The transistor device of claim 9 , wherein forming the gate dielectric layer comprises performing an in-situ steam generation (ISSG) process at a pressure of 1 Torr to 20 Torr.

13. The transistor device of claim 12 , wherein a temperature of the first process chamber is maintained at temperature of 500° C. to 700° C. prior to formation of the dielectric layer and 850° to 1050° C. during the formation of the dielectric layer.

14. The transistor device of claim 9 , wherein a third step of the at least two sequential process steps is a thermal process in O 2 at a temperature of 400° C. to 1200° C.

15. The transistor device of claim 9 , wherein a third step of the at least two sequential process steps is a thermal process in NO at a temperature of 400° C. to 1200° C.

16. The transistor device of claim 9 , further comprising forming a polysilicon layer over the dielectric layer in a fourth process chamber connected to the transfer chamber, wherein the substrate is transferred through the transfer chamber to the fourth process chamber under an ambient of uniform, laminar inert gas flow within the transfer chamber.

17. The transistor device of claim 9 , wherein the step of forming the gate dielectric layer deposits hafnium oxide.

18. The transistor device of claim 17 , wherein the another step of the at least two sequential process steps is performed in the presence of an oxygen source at a temperature between 400° C. and 1200° C.

19. The transistor device of claim 18 , wherein the oxygen source is O 2 , N 2 O, or NO.

20. The transistor device of claim 9 , wherein the gas distribution system and the second pumping element maintain a pressure of about 3 Torr to about 20 Torr in the transfer chamber during the transfer.

21. A transistor device having a gate dielectric, a gate electrode, a source region and a drain region, wherein the gate dielectric is formed by a process comprising the steps of:
depositing a

Assignees

• Texas Instruments Inc

Inventors

• Bevan Malcolm J
• Bu Haowen
• Niimi Hiroaki
• Alshareef Husam N

Classifications

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title