Reduction of power consumption in memory devices during refresh modes

Patent metadata

Field	Value
Publication number	US-9396784-B2
Application number	US-201213997959-A
Country	US
Kind code	B2
Filing date	Mar 27, 2012
Priority date	Mar 27, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

First claim

What is claimed is:

1. A system, comprising:
a memory device configured with an active mode to accommodate read/write operations or a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle;
at least one register resource configured to provide a first voltage level corresponding to the active mode or a second voltage level corresponding to the self-refresh mode, the second voltage level being less than the first voltage level; and
a voltage controller communicatively coupled to the memory device and the at least one register resource, the voltage controller configured to receive the first voltage level or the second voltage level from the at least one register resource and supply the memory device with the first voltage level for the active mode or the second voltage level for the self-refresh mode.

2. The system of claim 1 , wherein the at least one register resource further to provide a first tolerance range corresponding to the first voltage level or a second tolerance range corresponding to the second voltage level.

3. The system of claim 1 , wherein the first voltage level, the second voltage level, or both are programmable values in the at least one register resource.

4. The system of claim 2 , wherein the first tolerance range, the second tolerance range, or both are programmable values in the at least one register resource.

5. The system of claim 1 , wherein the at least one register resource comprises a mode register, a multipurpose register, and/or a serial presence detect module.

6. The system of claim 1 , wherein the voltage controller at least includes a first voltage signal line to supply the first voltage level or a second voltage signal line to supply the second voltage level, and the voltage controller is to switch between the first and second voltage signal lines in accordance with transitions between the active mode and the self-refresh mode.

7. A method, comprising:
configuring a memory device with an active mode to accommodate read/write operations or a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle;
storing a first voltage level or a second voltage level that is less than the first voltage level in at least one register resource; and
operating the memory device at the first voltage level during the active model, or
operating the memory device at the second voltage level during the self-refresh mode.

8. The method of claim 7 , further comprising storing a first tolerance range corresponding to the first voltage level or a second tolerance range corresponding to the second voltage level in the at least one register resource.

9. The method of claim 7 , wherein the first voltage level, the second voltage level, or both are programmable values in the at least one register resource.

10. The method of claim 8 , wherein the first tolerance range, the second tolerance range, or both are programmable values in the at least one register resource.

11. The method of claim 7 , wherein the at least one register resource comprises a mode register, a multipurpose register, and/or a serial presence detect module.

12. The method of claim 7 , wherein the at least one register resource is to provide the first voltage level or the second voltage level to a voltage regulator to drive memory device to operate at the first voltage level during the active mode or to operate at the second voltage level during the self-refresh mode.

13. The method of claim 12 , wherein the voltage regulator at least includes a first voltage signal line to supply the first voltage level or a second voltage signal line to supply the second voltage level, and the voltage regulator is to switch between the first and second voltage signal lines in accordance with transitions between the active mode and the self-refresh mode.

Assignees

• Cox Christopher E
• Bains Kuljit S
• Halbert John B
• Intel Corp

Inventors

• Cox Christopher E
• Bains Kuljit S
• Halbert John B

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C2211/4068

  Voltage or leakage in refresh operations · CPC title

• G11C2211/4065

  Low level details of refresh operations · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title