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Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device
US9105317B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105317-B2 |
| Application number | US-201213611867-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 12, 2012 |
| Priority date | Jan 13, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
First claim
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What is claimed is: 1. A memory system comprising: a memory controller; and a semiconductor memory device including, an output circuit configured to output data stored in a memory cell array to the memory controller via output pads; an on-die-termination (ODT) calibration circuit configured to calibrate termination resistances connected to the output pads; and an output voltage level calibration circuit configured to, generate a reference voltage based on driving informati…
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- G11C7/1057Primary
Physics · mapped topic
Physics · mapped topic
Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9105317B2 cover?
- Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a refer…
- Who is the assignee on this patent?
- Eom Yoon-Joo, Jeon Young-Jin, Bae Yong-Cheol, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G11C7/1057. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).