Array substrate and liquid crystal display module including TFT having improved mobility and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9391099-B2
Application number	US-201414276903-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	Feb 15, 2008
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

An array substrate for a liquid crystal display device includes a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode; an active layer of intrinsic amorphous silicon on the gate insulating layer and corresponding to the gate electrode; an ohmic contact layer of impurity-doped amorphous silicon on the active layer; a data line crossing the gate line; a source electrode on the ohmic contact layer and connected to the data line; a drain electrode on the ohmic contact layer and spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing a portion of the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the drain contact hole.

First claim

What is claimed is:

1. An array substrate for a liquid crystal display device, comprising:
a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
a semiconductor layer including an active layer of intrinsic amorphous silicon and an ohmic contact layer of impurity doped amorphous silicon;
a data line crossing the gate line;
a source electrode on the ohmic contact layer and connected to the data line;
a drain electrode on the ohmic contact layer and spaced apart from the source electrode;
a passivation layer on the source electrode and the drain electrode and including a drain contact hole exposing a portion of the drain electrode;
a pixel electrode on the passivation layer and connected to the drain electrode through the drain contact hole; and
a metal oxide layer on the ohmic contact layer and only in a space between the source electrode and the drain electrode,
wherein the active layer is disposed on the gate insulating layer,
wherein the ohmic contact layer is disposed between the active layer and the source and drain electrodes,
wherein the metal oxide layer contacts an upper surface of the ohmic contact layer in a region over a center of the gate electrode, and the ohmic layer contacts the active layer, and
wherein the ohmic contact layer covers an entire top surface of the active layer in the space between the source electrode and the drain electrode.

2. The array substrate according to claim 1 , wherein the active layer has substantially the same thickness as the ohmic contact layer.

3. The array substrate according to claim 1 , wherein the active layer has a thickness of about 100 angstroms to about 700 angstroms, and the ohmic contact layer has a thickness of about 50 angstroms to about 500 angstroms.

4. The array substrate according to claim 1 , wherein each of the active layer and the ohmic contact layer has an island shape.

5. The array substrate according to claim 1 , wherein the pixel electrode overlaps a previous gate line to form a storage capacitor.

6. The array substrate according to claim 5 , further comprising a metal pattern overlapping the previous gate line and the pixel electrode and disposed on the gate insulating layer, wherein the metal pattern is connected to one of the previous gate line and the pixel electrode.

7. The array substrate according to claim 1 , wherein the source and drain electrodes contact the upper surface of the ohmic contact layer in a region over an edge of the gate electrode.

8. A liquid crystal display module, comprising:
a liquid crystal panel including an array substrate and a color filter substrate, the array substrate including:
a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
an active layer of intrinsic amorphous silicon on the gate insulating layer and corresponding to the gate electrode;
an ohmic contact layer of impurity-doped amorphous silicon on the active layer;
a data line crossing the gate line;
a source electrode on the ohmic contact layer and connected to the data line;
a drain electrode on the ohmic contact layer and spaced apart from the source electrode;
a passivation layer on the source electrode and drain electrode and including a drain contact hole exposing a portion of the drain electrode;
a pixel electrode on the passivation layer and connected to the drain electrode through the drain contact hole; and
a metal oxide layer on the ohmic contact layer and only in a space between the source electrode and the drain electrode,
wherein the ohmic contact layer covers an entire top surface of the active layer in the space between the source electrode and the drain electrode,
wherein the source and drain electrodes contact an upper surface of the ohmic contact layer, and
wherein the metal oxide layer contacts an upper surface of the ohmic contact layer in a region over a center of the gate electrode.

9. The liquid crystal display module according to claim 8 , wherein the active layer has substantially the same thickness as the ohmic contact layer.

10. The liquid crystal display module according to claim 8 , wherein the active layer has a thickness of about 100 angstroms to about 700 angstroms, and the ohmic contact layer has a thickness of about 50 angstroms to about 500 angstroms.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Cheol-Se
• Jo Jae-Hyung
• Yoo Duk-Keun

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title