Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9390995-B2
Application number	US-201214370803-A
Country	US
Kind code	B2
Filing date	Jul 25, 2012
Priority date	Jan 31, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a metallic base plate on which a fin arranged in a standing condition and a convex wall arranged in a standing condition are formed on a first main face by integral processing;
an insulating layer formed on a second main face of said base plate, the second main face being opposite to the first main face of said base plate;
a circuit pattern fixed to said insulating layer;
a semiconductor element joined to said circuit pattern; and
a sealing resin which seals said insulating layer, said circuit pattern, and said semiconductor element,
wherein said fin is formed with a slit that passes through in a thickness direction of said fin,
a margin of width is provided on said first main face of said base plate to surround said fin,
a side of said base plate is covered with said sealing resin all around but said margin of width of said base plate is laid open to said sealing resin,
said convex wall is lower than said fin in height,
and a linkage fin is swaged to be fixed between said convex wall and said fin,
and further wherein an indentation is produced on a base of said slit that passes through in said thickness direction of said fin.

2. The semiconductor device according to claim 1 , wherein said insulating layer includes inorganic powder.

3. The semiconductor device according to claim 1 , wherein said fin is formed in plural on said base plate by integral processing and the thickness of said fins in the plural is larger than the interval between said fins.

4. The semiconductor device according to claim 1 , wherein the slit is formed at the center of said fin.

5. The semiconductor device according to claim 1 , wherein at least a part of said semiconductor element is formed by a wide band gap semiconductor, said wide band gap semiconductor is any semiconductor of silicon carbide, gallium nitride-based material, or diamond.

6. The semiconductor device according to claim 1 ;
said base plate has a concave wall made of the two neighboring convex walls.

7. A semiconductor device comprising:
a metallic base plate on which a fin arranged in a standing condition is formed on a first main face by integral processing;
an insulating layer formed on a second main face of said base plate, the second main face being opposite to the first main face of said base plate;
a circuit pattern fixed to said insulating layer;
a semiconductor element joined to said circuit pattern; and
a sealing resin which seals said insulating layer, said circuit pattern, and said semiconductor element,
wherein said fin is formed with a slit that passes through in a thickness direction of said fin,
said base plate is formed, on the first main face, with a margin of width which surrounds said fin,
a side of said base plate is covered with the sealing resin, and said margin of width of said base plate is laid open to the sealing resin,
and further wherein an indentation is produced on a base of said slit that passes through in said thickness direction of said fin.

8. The semiconductor device according to claim 7 ,
wherein said insulating layer includes inorganic powder.

9. The semiconductor device according to claim 7 ,
wherein said fin is formed in plural on said base plate by integral processing and the thickness of said fins in the plural is larger than the interval between said fins.

10. The semiconductor device according to claim 7 ,
wherein the slit is formed at the center of said fin.

11. The semiconductor device according to claim 7 ,
wherein at least a part of said semiconductor element is formed by a wide band gap semiconductor, said wide band gap semiconductor is any semiconductor of silicon carbide, gallium nitride-based material, or diamond.

12. The method of manufacturing a semiconductor device according to claim 7 , wherein said base plate has a concave wall made of the two neighboring convex walls.

13. A method of manufacturing a semiconductor device, said method comprising:
a step of forming a metallic base plate on which a fin and a convex wall are arranged in a standing condition by integral processing, said fin being formed to with a slit that passes in a thickness direction of said fin, said base plate having a margin of width arranged at an outer peripheral end portion to surround said fin and said convex wall being lower than said fin in height,
a step of fixing a semiconductor element to said base plate;
a step of placing said base plate on which said semiconductor element is fixed, with said fin and said convex wall facing the downside, on a lower die in which a partition portion arranged in a standing condition from a base of a hollow portion is located at a position corresponding to said slit;
a step of overlaying an upper die on said lower die, on which said base plate is placed with said margin of width of said base plate keeping in contact with an upper face of said hollow portion of said lower die, to make a molding die and sealing a molding resin to said molding die;
a step of hardening said sealed molding resin by heating; and
a step of swaging a linkage fin between said convex wall and said fin to be fixed, after said molding resin is hardened,
wherein a height of the said fin is smaller than a depth of the hollow portion and a height of the partition portion.

14. The method of manufacturing the semiconductor device according to claim 13 , wherein the end of said partition portion is made to be flat.

15. The method of manufacturing the semiconductor device according to claim 13 , wherein the end of said partition portion is made to be a circular arc.

16. The method of manufacturing the semiconductor device according to claim 13 , wherein the end of said partition portion is made to be a sharp angle.

17. The method of manufacturing a semiconductor device according to claim 13 , wherein said base plate has a concave wall made of the two neighboring convex walls.

18. A method of manufacturing a semiconductor device, said method comprising:
a step of forming a metallic base plate on which a fin is arranged in a standing condition by integral processing, said fin being formed with a slit that passes in a thickness direction of said fin, the base plate having a margin of width arranged at an outer peripheral end portion, and the margin of width surrounding said fin;
a step of fixing a semiconductor element to said base plate;
a step of placing said base plate on which said semiconductor element is fixed, with said fin and said margin of width facing the downside, on a lower die in which a partition portion arranged in a standing condition from a base of a hollow portion is located at a position corresponding to said slit;
a step of overlaying a upper die on said lower die, on which said base plate is placed with said margin of width of said base plate keeping in contact with an upper face of said hollow portion of said lower die, to make a molding die and sealing a molding resin to said molding die; and
a step of hardening said sealed molding resin by heating,
wherein a height of the said fin is smaller than a depth of said hollow portion and a height of said partition portion.

19. The method of manufacturing a semiconductor device according to claim 18 , wherein said base plate has a concave wall made of the two neighboring convex walls.

Assignees

• Yamamoto Kei
• Tada Kazuhiro
• Komori Hideki
• Kimura Toru
• Goto Masaki
• Yoshihara Hiroyuki
• Mitsubishi Electric Corp

Inventors

• Yamamoto Kei
• Tada Kazuhiro
• Komori Hideki
• Kimura Toru
• Goto Masaki
• Yoshihara Hiroyuki

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/016

  using moulds · CPC title