Method, system, and apparatus for preparing substrates and bonding semiconductor layers to substrates

Patent metadata

Field	Value
Publication number	US-9390942-B2
Application number	US-201313831067-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Nov 30, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A method for reducing a concentration of particular surface contaminants from a surface of an insulating substrate of a semiconductor architecture prior to bonding with another layer, the insulating substrate being substantially non-diffusive to the particular surface contaminants, the method including:
depositing a semiconductor layer on the surface of the insulating substrate surface having a first concentration of the particular surface contaminants;
based on the depositing, diffusing a portion of the particular surface contaminants into the semiconductor layer;
based on the diffusing, removing the portion of the particular substrate contaminants from the surface of the insulating substrate, and
removing the deposited semiconductor layer from the surface of the insulating substrate, thereby obtaining a second concentration of the particular surface contaminants on the surface of the insulating substrate, the second concentration being substantially lower than the first concentration.

2. The method of claim 1 , wherein the deposited semiconductor layer has a second diffusion level, the insulating substrate has a first diffusion level, and the second diffusion level is greater than the first diffusion level.

3. The method of claim 1 , further comprising annealing the deposited semiconductor layer prior to removal.

4. The method of claim 3 , wherein the portion of the particular surface contaminants comprise a first portion and a second portion, the first portion of the particular surface contaminants diffusing into the deposited semiconductor layer during its deposition on the insulating substrate surface and the second portion of the particular surface contaminants further diffusing into the deposited semiconductor layer during annealing.

5. The method of claim 1 , wherein the particular surface contaminants include one or more of a transition metal, an alkali metal, a non-metal, and a metalloid.

6. The method of claim 1 , wherein the particular surface contaminants include a transition metal.

7. The method of claim 1 , wherein the insulating substrate has a level of surface damage and the surface damage level is reduced after removal of the deposited semiconductor layer.

8. The method of claim 1 , wherein the deposited semiconductor layer consists primarily of polysilicon.

9. The method of claim 1 , wherein the insulating substrate consists primarily of Sapphire.

10. A method for removing particular surface contaminants from a surface of a substantially non-diffusive insulating substrate to the particular surface contaminants, the insulating substrate having a first diffusion level, the method including:
depositing a layer of material on the surface of the insulating substrate, the material having a second diffusion level, the second diffusion level greater than the first diffusion level;
based on the depositing. diffusing a portion of the particular surface contaminants into the deposited layer of material:
based on the diffusing. removing the portion of the particular surface contaminants from the surface of the insulating substrate; and
removing the layer of deposited material from the surface of the insulating layer.

11. The method of claim 10 , further comprising annealing the deposited material layer prior to removal.

12. The method of claim 11 , wherein the portion of the particular surface contaminants comprise a first portion and a second portion, the first portion of the particular surface contaminants diffusing into the deposited material layer during its deposition on the insulating substrate surface and the second portion of the particular surface contaminants further diffusing into the deposited material layer during the annealing.

13. The method of claim 12 , wherein the particular surface contaminants include one or more of a transition metal, an alkali metal, a non-metal, and a metalloid.

14. The method of claim 12 , wherein the particular surface contaminants include a transition metal.

15. The method of claim 10 , wherein the insulating substrate has a level of surface damage and the surface damage level is reduced after removal of the deposited material layer.

16. The method of claim 10 , wherein the deposited material layer consists primarily of a semiconductor.

17. The method of claim 10 , wherein the deposited material layer consists primarily of polysilicon.

18. The method of claim 10 , wherein the insulating substrate consists primarily of Sapphire.

19. A method of forming a semiconductor architecture including an insulating substrate bonded to an electrically active semiconductor layer, the method including:
removing a portion of particular surface contaminants from the surface of the insulating substrate, the insulating substrate being substantially non-diffusive to the particular surface contaminants, the removing comprising the steps of:
depositing a layer of material on the insulating substrate surface, wherein the material has a second diffusion level, the insulating substrate has a first diffusion level; and the second diffusion level is greater than the first diffusion level;
(ii) based on the depositing, diffusing a portion of the particular surface contaminants into the deposited layer of material;
(iii) based on the diffusing, removing the portion of the particular surface contaminants from the surface of the insulatging substrate; and
(iv) removing the layer of deposited material from the insulating substrate surface.

20. The method of forming a semiconductor architecture including an insulating substrate of claim 19 , the removing of the particular surface contaminants step further comprising annealing the deposited material layer prior to removal.

21. The method of forming a semiconductor architecture including an insulating substrate of claim 20 , wherein the portion of the particular surface contaminants comprise a first portion and a second portion, the first portion of the particular surface contaminants diffuse into the deposited material layer during its deposition on the insulating substrate surface and second portion of the particular surface contaminants further diffuse into the deposited material layer during the annealing.

22. The method of forming a semiconductor architecture including an insulating substrate of claim 21 , wherein the particular surface contaminants include one or more of a transition metal, an alkali metal, a non-metal, and a metalloid.

23. The method of forming a semiconductor architecture including an insulating substrate of claim 21 , wherein the particular surface contaminants include a transition metal.

24. The method of forming a semiconductor architecture including an insulating substrate of claim 19 , wherein the insulating substrate has a level of surface damage and the surface damage level is reduced after removal of the deposited material layer.

25. The method of forming a semiconductor architecture including an insulating substrate of claim 19 , wherein the deposited material layer consists primarily of a semiconductor.

26. The method of forming a semiconductor architecture including an insulating substrate of claim 19 , wherein the deposited material layer consists primarily of polysilicon.

27. The method of forming a semiconductor architecture including an insulating substrate of claim 19 , wherein the insulating substrate consists primarily of Sapphire.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Domyo Hiroshi
• Mccafferty Michael
• Duvallet Alain
• Sato Masaki
• O'Brien Christopher
• Miscione Anthony Mark
• Imthurn George

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P36/03

  within silicon bodies · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P70/15

  by wet cleaning only (H10P70/52 takes precedence) · CPC title