Transistor, semiconductor device, and semiconductor structure
US-2024379874-A1 · Nov 14, 2024 · US
Integrated circuit including DRAM and SRAM/logic
US8994085B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994085-B2 |
| Application number | US-201213551714-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 18, 2012 |
| Priority date | Jan 6, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising field effect transistors (FETs) at least some of which comprise a part of random access memory (RAM) and logic devices, comprising: an N+ type layer; a buffer layer arranged on and in contact with the N+ type layer; a P type region formed on and in contact with the buffer layer; an insulator layer overlying the N+ type layer; a silicon layer overlying the insulator layer; an embedded dynamic RAM FET formed in the si…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10D86/01Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994085B2 cover?
- An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type …
- Who is the assignee on this patent?
- Basker Veeraraghavan S, Cheng Kangguo, Doris Bruce B, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification H10D86/01. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).