Integrated circuits and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-9385213-B2
Application number	US-201213722142-A
Country	US
Kind code	B2
Filing date	Dec 20, 2012
Priority date	May 26, 2010
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor;
forming a first drain region and a first source region for the first type transistor in the first diffusion area;
forming a second drain region and a second source region for the second type transistor in the second diffusion area;
forming a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction; and
forming a first metallic layer, a second metallic layer, and a third metallic layer, wherein the first metallic layer is electrically coupled with the first source region, the second metallic layer is electrically coupled with the first drain region and the second drain region, the third metallic layer is electrically coupled with the second source region, the first metallic layer and the first diffusion area are overlapped by a first distance in the routing direction, the second metallic layer and the first diffusion area are overlapped by a second distance in the routing direction, the first distance is larger than the second distance, the third metallic layer and the second diffusion area are overlapped by a third distance in the routing direction, the second metallic layer and the second diffusion area are overlapped by a fourth distance in the routing direction, and the third distance is larger than the fourth distance.

2. The method of claim 1 , wherein the first diffusion area has a first width, a ratio of the first distance to the first width is between about 0.75:1 to about 1:1, and a ratio of the second distance to the first width is between about 0.1:1 to about 0.33:1.

3. The method of claim 1 , wherein the second diffusion area has a second width, a ratio of the third distance to the second width is between about 0.75:1 to about 1:1, and a ratio of the fourth distance to the second width is between about 0.1:1 to about 0.33:1.

4. The method of claim 1 , wherein the first metallic layer directly contacts the first source region, the second metallic layer directly contacts the first and second drain regions, and the third metallic layer directly contacts the second source region.

5. The method of claim 1 , further comprising:
forming a plurality of fourth metallic layers each directly contacting one of the first and second drain regions and the first and second source regions, wherein the plurality of fourth metallic layers each at least partially overlap one of the first, second, and third metallic layers in the routing direction.

6. The method of claim 5 , wherein the plurality of fourth metallic layers each substantially continuously extend, in the routing direction, from an edge to an opposite edge of the first diffusion area or the second diffusion area.

7. The method of claim 5 , wherein the plurality of fourth metallic layers each extends, in the routing direction, a distance equal to or greater than 95% of a width of the first diffusion area or the second diffusion area.

8. A method of forming a system, the method comprising:
forming an integrated circuit, wherein forming the integrate circuit comprises:
forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor;
forming a first drain region and a first source region for the first type transistor in the first diffusion area;
forming a second drain region and a second source region for the second type transistor in the second diffusion area;
forming a gate electrode continuously extending across the first diffusion area and the second diffusion area in a routing direction;
forming a first metallic layer, a second metallic layer, and a third metallic layer, wherein the first metallic layer is electrically coupled with the first source region, the second metallic layer is electrically coupled with the first drain region and the second drain region, the third metallic layer is electrically coupled with the second source region, the first metallic layer and the first diffusion area are overlapped by a first distance in the routing direction, the second metallic layer and the first diffusion area are overlapped by a second distance in the routing direction, the first distance is larger than the second distance, the third metallic layer and the second diffusion area are overlapped by a third distance in the routing direction, the second metallic layer and the second diffusion area are overlapped by a fourth distance in the routing direction, and the third distance is larger than the fourth distance; and

electrically coupling the integrated circuit to a substrate board.

9. The method of claim 8 , wherein forming the integrated circuit further comprises forming the first diffusion area to have a first width, a ratio of the first distance to the first width is between about 0.75:1 to about 1:1, and a ratio of the second distance to the first width is between about 0.1:1 to about 0.33:1; and
forming the second diffusion area to have a second width, a ratio of the third distance to the second width is between about 0.75:1 to about 1:1, and a ratio of the fourth distance to the second width is between about 0.1:1 to about 0.33:1.

10. The method of claim 8 , wherein forming the integrated circuit further comprises forming a plurality of fourth metallic layers each directly contacting one of the first and second drain regions and the first and second source regions, wherein the plurality of fourth metallic layers each at least partially overlap one of the first, second, and third metallic layers in the routing direction.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wu Chung-Cheng
• Keshavarzi Ali
• Fung Ka Hing
• Guo Ta-Pen
• Tzeng Jiann-Tyng
• Chen Yen-Ming
• Lin Shyue-Shyh
• Wang Shyh-Wei
• Yang Sheng-Jier
• Tseng Hsiang-Jen
• Scott David B
• Cao Min

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title