Deep trench isolation structure layout and method of forming

Patent metadata

Field	Value
Publication number	US-9385190-B2
Application number	US-201414196278-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Mar 4, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate; and
a plurality of deep trench isolation structures formed in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, wherein
each of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and where the second dimension is at least twice the first dimension,
the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction, and
the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that at least one second trench-isolated region is between consecutive first columns in the array, and wherein adjacent of the plurality of first columns and the second trench-isolated regions share common deep trench isolation structures in between, wherein each of first plurality of first trench-isolated regions includes a single semiconductor device formed within and wherein each of the second plurality of second trench-isolated regions includes at least two semiconductor devices formed within.

2. The semiconductor device of claim 1 wherein the single semiconductor device comprises a single diode and wherein the at least two semiconductor devices comprises at least one diode and at least one antifuse.

3. The semiconductor device of claim 1 wherein the plurality of deep trench isolation structures additionally define and surround a third plurality of third trench-isolated regions and a fourth plurality of fourth trench-isolated regions, the third plurality of third trench-isolated regions arranged in a column between columns of the fourth plurality of fourth trench-isolated regions, and wherein the third plurality of third trench-isolated regions are offset from the fourth plurality of fourth trench-isolated regions by an offset distance.

4. The semiconductor device of claim 3 wherein the third plurality of third trench-isolated regions are offset from the fourth plurality of fourth trench-isolated regions in the first direction.

5. The semiconductor device of claim 1 wherein the plurality of first columns are interleaved with the second trench-isolated regions along a second direction, and wherein the second direction is substantially perpendicular to the first direction.

6. The semiconductor device of claim 1 wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

7. The semiconductor device of claim 1 wherein each of the plurality of first trench-isolated regions are substantially identical in size.

8. An antifuse array, comprising:
a semiconductor substrate; and
a plurality of deep trench isolation structures formed in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, wherein
each of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and wherein the second dimension is at least twice the first dimension,
the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction,
the plurality of first columns are interleaved with the second plurality of second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array,
each of first plurality of first trench-isolated regions includes a single diode formed within, and
each of the second plurality of second trench-isolated regions includes at least one diode and at least one antifuse formed within.

9. The antifuse array of claim 8 wherein the plurality of deep trench isolation structures additionally define and surround a third plurality of third trench-isolated regions and a fourth plurality of fourth trench-isolated regions, the third plurality of third trench-isolated regions arranged in a column between columns of the fourth plurality of fourth trench-isolated regions, and wherein the third plurality of third trench-isolated regions are offset from the fourth plurality of fourth trench-isolated regions by an offset distance.

10. The antifuse array of claim 8 wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

11. The antifuse array of claim 8 wherein each of the plurality of first trench-isolated regions are substantially identical in size.

12. The antifuse array of claim 8 wherein each of the second plurality of second trench-isolated regions includes a plurality of diodes, each of the plurality of diodes having an anode, and wherein the anodes of the plurality of diodes in each second trench-isolated region are coupled together.

13. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate; and
forming a plurality of deep trench isolation structures in the semiconductor substrate, the plurality of deep trench isolation structures each extending at least to a buried insulator layer in the semiconductor substrate, the plurality of deep trench isolation structures defining and surrounding a first plurality of first trench-isolated regions in the substrate and a second plurality of second trench-isolated regions in the substrate, wherein
each of the first plurality of first trench-isolated regions has a first dimension along a first direction and each of the second plurality of second trench-isolated regions has a corresponding second dimension along the first direction, and wherein the second dimension is at least twice the first dimension,
the first plurality of first trench-isolated regions are arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions arranged along the first direction, and
wherein the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array, and wherein adjacent of the plurality of first columns and the second trench-isolated regions share common deep trench isolation structures in between; and

forming a single semiconductor device in each of first plurality of first trench-isolated regions and forming at least two semiconductor devices in each of

Assignees

• Freescale Semiconductor Inc

Inventors

• Pigott John M
• Rogers Brent D
• Gray Randall C

Classifications

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title